Please note: This is a beta version of the new dblp website.
You can find the classic dblp view of this page here.
You can find the classic dblp view of this page here.
Aarti Gupta
2010 – today
- 2013
[c94]Pranav Garg, Franjo Ivancic, Gogul Balakrishnan, Naoto Maeda, Aarti Gupta: Feedback-directed unit test generation for C/C++ using concolic execution. ICSE 2013: 132-141- 2012
- [j13]Sandip Ray, Jayanta Bhadra, Magdy S. Abadir, Li-C. Wang, Aarti Gupta: Introduction to special section on verification challenges in the concurrent world. ACM Trans. Design Autom. Electr. Syst. 17(3): 19 (2012)
- [c93]Niloofar Razavi, Franjo Ivancic, Vineet Kahlon, Aarti Gupta: Concurrent Test Generation Using Concolic Multi-trace Analysis. APLAS 2012: 239-255
- [c92]Jing Yang, Gogul Balakrishnan, Naoto Maeda, Franjo Ivancic, Aarti Gupta, Nishant Sinha, Sriram Sankaranarayanan, Naveen Sharma: Object Model Construction for Inheritance in C++ and Its Applications to Program Analysis. CC 2012: 144-164
- [c91]Arnab Sinha, Sharad Malik, Aarti Gupta: Efficient predictive analysis for detecting nondeterminism in multi-threaded programs. FMCAD 2012: 6-15
- [c90]V. M. Achutha KiranKumar, Aarti Gupta, Rajnish Ghughal: Symbolic Trajectory Evaluation: The primary validation Vehicle for next generation Intel® Processor Graphics FPU. FMCAD 2012: 149-156
- [c89]Khalil Ghorbal, Parasara Sridhar Duggirala, Vineet Kahlon, Franjo Ivancic, Aarti Gupta: Efficient Probabilistic Model Checking of Systems with Ranged Probabilities. RP 2012: 107-120
- [c88]Malay K. Ganai, Dongyoon Lee, Aarti Gupta: DTAM: dynamic taint analysis of multi-threaded programs for relevancy. SIGSOFT FSE 2012: 46
- [c87]Khalil Ghorbal, Franjo Ivancic, Gogul Balakrishnan, Naoto Maeda, Aarti Gupta: Donut Domains: Efficient Non-convex Domains for Abstract Interpretation. VMCAI 2012: 235-250
- 2011
- [j12]Chao Wang, Sudipta Kundu, Rhishikesh Limaye, Malay K. Ganai, Aarti Gupta: Symbolic predictive analysis for concurrent programs. Formal Asp. Comput. 23(6): 781-805 (2011)
- [c86]Prakash Prabhu, Naoto Maeda, Gogul Balakrishnan, Franjo Ivancic, Aarti Gupta: Interprocedural Exception Analysis for C++. ECOOP 2011: 583-608
- [c85]
- [c84]Gogul Balakrishnan, Naoto Maeda, Sriram Sankaranarayanan, Franjo Ivancic, Aarti Gupta, Rakesh Pothengil: Modeling and Analyzing the Interaction of C and C++ Strings. FoVeOOS 2011: 67-85
- [c83]Arnab Sinha, Sharad Malik, Chao Wang, Aarti Gupta: Predicting Serializability Violations: SMT-Based Search vs. DPOR-Based Search. Haifa Verification Conference 2011: 95-114
- [c82]Chao Wang, Mahmoud Said, Aarti Gupta: Coverage guided systematic concurrency testing. ICSE 2011: 221-230
- [c81]Franjo Ivancic, Gogul Balakrishnan, Aarti Gupta, Sriram Sankaranarayanan, Naoto Maeda, Hiroki Tokuoka, Takashi Imoto, Yoshiaki Miyazaki: DC2: A framework for scalable, scope-bounded software verification. ASE 2011: 133-142
- [c80]Malay K. Ganai, Nipun Arora, Chao Wang, Aarti Gupta, Gogul Balakrishnan: BEST: A symbolic testing tool for predicting multi-threaded program failures. ASE 2011: 596-599
- [c79]Arnab Sinha, Sharad Malik, Chao Wang, Aarti Gupta: Predictive analysis for detecting serializability violations through Trace Segmentation. MEMOCODE 2011: 99-108
- 2010
- [c78]Sicun Gao, Malay K. Ganai, Franjo Ivancic, Aarti Gupta, Sriram Sankaranarayanan, Edmund M. Clarke: Integrating ICP and LRA solvers for deciding nonlinear real arithmetic problems. FMCAD 2010: 81-89
- [c77]Gogul Balakrishnan, Malay K. Ganai, Aarti Gupta, Franjo Ivancic, Vineet Kahlon, Weihong Li, Naoto Maeda, Nadia Papakonstantinou, Sriram Sankaranarayanan, Nishant Sinha, Chao Wang: Scalable and precise program analysis at NEC. FMCAD 2010: 273-274
- [c76]Truong Nghiem, Sriram Sankaranarayanan, Georgios E. Fainekos, Franjo Ivancic, Aarti Gupta, George J. Pappas: Monte-carlo techniques for falsification of temporal properties of non-linear hybrid systems. HSCC 2010: 211-220
- [c75]Franjo Ivancic, Malay K. Ganai, Sriram Sankaranarayanan, Aarti Gupta: Numerical stability analysis of floating-point computations using software model checking. MEMOCODE 2010: 49-58
- [c74]William R. Harris, Sriram Sankaranarayanan, Franjo Ivancic, Aarti Gupta: Program analysis via satisfiability modulo path programs. POPL 2010: 71-82
- [c73]Chao Wang, Rhishikesh Limaye, Malay K. Ganai, Aarti Gupta: Trace-Based Symbolic Analysis for Atomicity Violations. TACAS 2010: 328-342
2000 – 2009
- 2009
- [j11]
- [j10]Zijiang Yang, Chao Wang, Aarti Gupta, Franjo Ivancic: Model checking sequential software programs via mixed symbolic analysis. ACM Trans. Design Autom. Electr. Syst. 14(1) (2009)
- [c72]Vineet Kahlon, Chao Wang, Aarti Gupta: Monotonic Partial Order Reduction: An Optimal Symbolic Partial Order Reduction Technique. CAV 2009: 398-413
- [c71]Gogul Balakrishnan, Sriram Sankaranarayanan, Franjo Ivancic, Aarti Gupta: Refining the control structure of loops using static analysis. EMSOFT 2009: 49-58
- [c70]Chao Wang, Sudipta Kundu, Malay K. Ganai, Aarti Gupta: Symbolic Predictive Analysis for Concurrent Programs. FM 2009: 256-272
- [c69]Georgios E. Fainekos, Sriram Sankaranarayanan, Franjo Ivancic, Aarti Gupta: Robustness of Model-Based Simulations. RTSS 2009: 345-354
- [c68]Chao Wang, Swarat Chaudhuri, Aarti Gupta, Yu Yang: Symbolic pruning of concurrent program executions. ESEC/SIGSOFT FSE 2009: 23-32
- [c67]Vineet Kahlon, Sriram Sankaranarayanan, Aarti Gupta: Semantic Reduction of Thread Interleavings in Concurrent Programs. TACAS 2009: 124-138
- [c66]
- 2008
- [j9]Aleksandr Zaks, Zijiang Yang, Ilya Shlyakhter, Franjo Ivancic, Srihari Cadambi, Malay K. Ganai, Aarti Gupta, Pranav Ashar: Bitwidth Reduction via Symbolic Interval Analysis for Software Model Checking. IEEE Trans. on CAD of Integrated Circuits and Systems 27(8): 1513-1517 (2008)
- [j8]Franjo Ivancic, Zijiang Yang, Malay K. Ganai, Aarti Gupta, Pranav Ashar: Efficient SAT-based bounded model checking for software verification. Theor. Comput. Sci. 404(3): 256-274 (2008)
- [c65]Chao Wang, Yu Yang, Aarti Gupta, Ganesh Gopalakrishnan: Dynamic Model Checking with Property Driven Pruning to Detect Race Conditions. ATVA 2008: 126-140
- [c64]Aarti Gupta: Software Verification: Roles and Challenges for Automatic Decision Procedures. IJCAR 2008: 1
- [c63]
- [c62]Malay K. Ganai, Aarti Gupta: Completeness in SMT-based BMC for Software Programs. DATE 2008: 831-836
- [c61]Sriram Sankaranarayanan, Franjo Ivancic, Aarti Gupta: Mining library specifications using inductive logic programming. ICSE 2008: 131-140
- [c60]Sriram Sankaranarayanan, Swarat Chaudhuri, Franjo Ivancic, Aarti Gupta: Dynamic inference of likely data preconditions over predicates by tree learning. ISSTA 2008: 295-306
- [c59]Gogul Balakrishnan, Sriram Sankaranarayanan, Franjo Ivancic, Ou Wei, Aarti Gupta: SLR: Path-Sensitive Analysis through Infeasible-Path Detection and Syntactic Language Refinement. SAS 2008: 238-254
- [c58]Fang Yu, Chao Wang, Aarti Gupta, Tevfik Bultan: Modular verification of web services using efficient symbolic encoding and summarization. SIGSOFT FSE 2008: 192-202
- [c57]
- [c56]Chao Wang, Zijiang Yang, Vineet Kahlon, Aarti Gupta: Peephole Partial Order Reduction. TACAS 2008: 382-396
- [e1]Aarti Gupta, Sharad Malik (Eds.): Computer Aided Verification, 20th International Conference, CAV 2008, Princeton, NJ, USA, July 7-14, 2008, Proceedings. Lecture Notes in Computer Science 5123, Springer 2008, ISBN 978-3-540-70543-7
- 2007
- [j7]Malay K. Ganai, Muralidhar Talupur, Aarti Gupta: SDSAT: Tight Integration of Small Domain Encoding and Lazy Approaches in Solving Difference Logic. JSAT 3(1-2): 91-114 (2007)
- [j6]Chao Wang, Zijiang Yang, Franjo Ivancic, Aarti Gupta: Disjunctive image computation for software verification. ACM Trans. Design Autom. Electr. Syst. 12(2) (2007)
- [c55]Malay K. Ganai, Aarti Gupta: Efficient BMC for Multi-Clock Systems with Clocked Specifications. ASP-DAC 2007: 310-315
- [c54]Vineet Kahlon, Yu Yang, Sriram Sankaranarayanan, Aarti Gupta: Fast and Accurate Static Data-Race Detection for Concurrent Programs. CAV 2007: 226-239
- [c53]Chao Wang, Zijiang Yang, Aarti Gupta, Franjo Ivancic: Using Counterexamples for Improving the Precision of Reachability Computation with Polyhedra. CAV 2007: 352-365
- [c52]Chao Wang, Aarti Gupta, Franjo Ivancic: Induction in CEGAR for Detecting Counterexamples. FMCAD 2007: 77-84
- [c51]Aarti Gupta: From Hardware Verification to Software Verification: Re-use and Re-learn. Haifa Verification Conference 2007: 14-15
- [c50]Chao Wang, Hyondeuk Kim, Aarti Gupta: Hybrid CEGAR: combining variable hiding and predicate abstraction. ICCAD 2007: 310-317
- [c49]Aarti Gupta, Tim Oates: Using Ontologies and the Web to Learn Lexical Semantics. IJCAI 2007: 1618-1623
- [c48]
- [c47]Sriram Sankaranarayanan, Franjo Ivancic, Aarti Gupta: Program Analysis Using Symbolic Ranges. SAS 2007: 366-383
- [c46]Malay K. Ganai, Akira Mukaiyama, Aarti Gupta, Kazutoshi Wakabayashi: Synthesizing "Verification Aware" Models: Why and How? VLSI Design 2007: 50-56
- [i1]Malay K. Ganai, Aarti Gupta, Pranav Ashar: Verification of Embedded Memory Systems using Efficient Memory Modeling. CoRR abs/0710.4666 (2007)
- 2006
- [j5]Malay K. Ganai, Aarti Gupta, Zijiang Yang, Pranav Ashar: Efficient distributed SAT and SAT-based distributed Bounded Model Checking. STTT 8(4-5): 387-396 (2006)
- [c45]Chao Wang, Zijiang Yang, Franjo Ivancic, Aarti Gupta: Whodunit? Causal Analysis for Counterexamples. ATVA 2006: 82-95
- [c44]Himanshu Jain, Franjo Ivancic, Aarti Gupta, Ilya Shlyakhter, Chao Wang: Using Statically Computed Invariants Inside the Predicate Abstraction and Refinement Loop. CAV 2006: 137-151
- [c43]Vineet Kahlon, Aarti Gupta, Nishant Sinha: Symbolic Model Checking of Concurrent Programs Using Partial Orders and On-the-Fly Transactions. CAV 2006: 286-299
- [c42]Chao Wang, Aarti Gupta, Malay K. Ganai: Predicate learning and selective theory deduction for a difference logic solver. DAC 2006: 235-240
- [c41]Chao Wang, Zijiang Yang, Franjo Ivancic, Aarti Gupta: Disjunctive image computation for embedded software verification. DATE 2006: 1205-1210
- [c40]
- [c39]Vineet Kahlon, Aarti Gupta: An Automata-Theoretic Approach for Model Checking Threads for LTL Propert. LICS 2006: 101-110
- [c38]Zijiang Yang, Chao Wang, Aarti Gupta, Franjo Ivancic: Mixed symbolic representations for model checking software programs. MEMOCODE 2006: 17-26
- [c37]Sriram Sankaranarayanan, Franjo Ivancic, Ilya Shlyakhter, Aarti Gupta: Static Analysis in Disjunctive Numerical Domains. SAS 2006: 3-17
- [c36]Aarti Gupta, Malay K. Ganai, Chao Wang: SAT-Based Verification Methods and Applications in Hardware Verification. SFM 2006: 108-143
- [c35]Malay K. Ganai, Muralidhar Talupur, Aarti Gupta: SDSAT: Tight Integration of Small Domain Encoding and Lazy Approaches in a Separation Logic Solver. TACAS 2006: 135-150
- 2005
- [j4]Mukul R. Prasad, Armin Biere, Aarti Gupta: A survey of recent advances in SAT-based formal verification. STTT 7(2): 156-173 (2005)
- [p1]Aarti Gupta, Ali Alphan Bayazit, Yogesh S. Mahajan: Verification Languages. The Industrial Information Technology Handbook 2005: 1-18
- [c34]Daijue Tang, Sharad Malik, Aarti Gupta, C. Norris Ip: Symmetry Reduction in SAT-Based Model Checking. CAV 2005: 125-138
- [c33]Franjo Ivancic, Zijiang Yang, Malay K. Ganai, Aarti Gupta, Ilya Shlyakhter, Pranav Ashar: F-Soft: Software Verification Platform. CAV 2005: 301-306
- [c32]Vineet Kahlon, Franjo Ivancic, Aarti Gupta: Reasoning About Threads Communicating via Locks. CAV 2005: 505-518
- [c31]Malay K. Ganai, Aarti Gupta, Pranav Ashar: Beyond safety: customized SAT-based model checking. DAC 2005: 738-743
- [c30]Malay K. Ganai, Aarti Gupta, Pranav Ashar: Verification of Embedded Memory Systems using Efficient Memory Modeling. DATE 2005: 1096-1101
- [c29]Franjo Ivancic, Ilya Shlyakhter, Aarti Gupta, Malay K. Ganai: Model Checking C Programs Using F-SOFT. ICCD 2005: 297-308
- [c28]Chao Wang, Franjo Ivancic, Malay K. Ganai, Aarti Gupta: Deciding Separation Logic Formulae by SAT and Incremental Negative Cycle Elimination. LPAR 2005: 322-336
- [c27]Himanshu Jain, Franjo Ivancic, Aarti Gupta, Malay K. Ganai: Localization and Register Sharing for Predicate Abstraction. TACAS 2005: 397-412
- [c26]Malay K. Ganai, Aarti Gupta, Pranav Ashar: DiVer: SAT-Based Model Checking Platform for Verifying Large Scale Systems. TACAS 2005: 575-580
- [c25]Aarti Gupta, Malay K. Ganai, Pranav Ashar: Lazy Constraints and SAT Heuristics for Proof-Based Abstraction. VLSI Design 2005: 183-188
- 2004
- [c24]Malay K. Ganai, Aarti Gupta, Pranav Ashar: Efficient Modeling of Embedded Memories in Bounded Model Checking. CAV 2004: 440-452
- [c23]Malay K. Ganai, Aarti Gupta, Pranav Ashar: Efficient SAT-based unbounded symbolic model checking using circuit cofactoring. ICCAD 2004: 510-517
- [c22]Pranav Ashar, Malay K. Ganai, Aarti Gupta, Franjo Ivancic, Zijiang Yang: Efficient SAT-based Bounded Model Checking for Software Verification. ISoLA (Preliminary proceedings) 2004: 157-164
- 2003
- [c21]Aarti Gupta, Malay K. Ganai, Chao Wang, Zijiang Yang, Pranav Ashar: Abstraction and BDDs Complement SAT-Based BMC in DiVer. CAV 2003: 206-209
- [c20]Malay K. Ganai, Aarti Gupta, Zijiang Yang, Pranav Ashar: Efficient Distributed SAT and SAT-Based Distributed Bounded Model Checking. CHARME 2003: 334-347
- [c19]Aarti Gupta, Malay K. Ganai, Chao Wang, Zijiang Yang, Pranav Ashar: Learning from BDDs in SAT-based bounded model checking. DAC 2003: 824-829
- [c18]Aarti Gupta, Malay K. Ganai, Zijiang Yang, Pranav Ashar: Iterative Abstraction using SAT-based BMC with Proof Analysis. ICCAD 2003: 416-423
- 2002
- [j3]Aarti Gupta: Assertion-based verification turns the corner. IEEE Design & Test of Computers 19(4): 131-132 (2002)
- [c17]Malay K. Ganai, Pranav Ashar, Aarti Gupta, Lintao Zhang, Sharad Malik: Combining strengths of circuit-based and CNF-based algorithms for a high-performance SAT solver. DAC 2002: 747-750
- [c16]Aarti Gupta, Albert E. Casavant, Pranav Ashar, X. G. Liu, Akira Mukaiyama, Kazutoshi Wakabayashi: Property-Specific Testbench Generation for Guided Simulation. VLSI Design 2002: 524-
- 2001
- [j2]Pranav Ashar, Aarti Gupta, Sharad Malik: Using complete-1-distinguishability for FSM equivalence checking. ACM Trans. Design Autom. Electr. Syst. 6(4): 569-590 (2001)
- [c15]Aarti Gupta, Anubhav Gupta, Zijiang Yang, Pranav Ashar: Dynamic Detection and Removal of Inactive Clauses in SAT with Application in Image Computation. DAC 2001: 536-541
- [c14]Albert E. Casavant, Aarti Gupta, S. Liu, Akira Mukaiyama, Kazutoshi Wakabayashi, Pranav Ashar: Property-specific witness graph generation for guided simulation. DATE 2001: 799
- [c13]Aarti Gupta, Zijiang Yang, Pranav Ashar, Lintao Zhang, Sharad Malik: Partition-Based Decision Heuristics for Image Computation Using SAT and BDDs. ICCAD 2001: 286-292
- 2000
- [c12]Aarti Gupta, Zijiang Yang, Pranav Ashar, Anubhav Gupta: SAT-Based Image Computation with Application in Reachability Analysis. FMCAD 2000: 354-371
- [c11]Aarti Gupta, Pranav Ashar: Fast Error Diagnosis for Combinational Verification. VLSI Design 2000: 442-448
1990 – 1999
- 1999
- [c10]Aarti Gupta, Pranav Ashar, Sharad Malik: Exploiting Retiming in a Guided Simulation Based Validation Methodology. CHARME 1999: 350-353
- [c9]Pranav Ashar, Anand Raghunathan, Aarti Gupta, Subhrajit Bhattacharya: Verification of Scheduling in the Presence of Loops Using Uninterpreted Symbolic Simulation. ICCD 1999: 458-466
- 1998
- [c8]Aarti Gupta, Pranav Ashar: Integrating a Boolean Satisfiability Checker and BDDs for Combinational Equivalence Checking. VLSI Design 1998: 222-225
- 1997
- [c7]Aarti Gupta, Sharad Malik, Pranav Ashar: Toward Formalizing a Validation Methodology Using Simulation Coverage. DAC 1997: 740-745
- 1996
- [c6]Pranav Ashar, Aarti Gupta, Sharad Malik: Using complete-1-distinguishability for FSM equivalence checking. ICCAD 1996: 346-353
- 1994
- [c5]Aarti Gupta, Allan L. Fisher: Tradeoffs in Canonical Sequential Function Representations. ICCD 1994: 111-116
- 1993
- [c4]Aarti Gupta, Allan L. Fisher: Parametric Circuit Representation Using Inductive Boolean Functions. CAV 1993: 15-28
- [c3]Aarti Gupta, Allan L. Fisher: Representation and symbolic manipulation of linearly inductive Boolean functions. ICCAD 1993: 192-199
- 1992
- [j1]Aarti Gupta: Formal Hardware Verification Methods: A Survey. Formal Methods in System Design 1(2/3): 151-238 (1992)
- 1990
- [c2]
1980 – 1989
- 1986
- [c1]Moon-Jung Chung, Edward J. Toy, Aarti Gupta: A Parallel Computer Based on Cube-Connected Cycles for Wafer-Scale. FJCC 1986: 325-334
Coauthor Index
data released under the ODC-BY 1.0 license. See also our legal information page
last updated on 2013-05-24 22:21 CEST by the dblp team