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 | 2013 | |
|---|---|---|
| c113 |      | Yue Gao, Sandeep K. Gupta, Melvin A. Breuer: Using explicit output comparisons for fault tolerant scheduling (FTS) on modern high-performance processors. DATE 2013: 927-932 |
| c112 | | Byeongju Cha, Sandeep K. Gupta: Trojan detection via delay measurements: a new approach to select paths and vectors to maximize effectiveness and minimize cost. DATE 2013: 1265-1270 |
| 2012 | ||
| c111 | | Byeongju Cha, Sandeep K. Gupta: Efficient Trojan Detection via Calibration of Process Variations. ATS 2012: 355-361 |
| c110 | | Hsunwei Hsiung, Byeongju Cha, Sandeep K. Gupta: Salvaging chips with caches beyond repair. DATE 2012: 1263-1268 |
| c109 | | |
| c108 | | Bin Liu, Hsunwei Hsiung, Da Cheng, Ramesh Govindan, Sandeep K. Gupta: Towards systematic roadmaps for networked systems. HotNets 2012: 91-96 |
| c107 | | Mohammad Mirza-Aghatabar, Melvin A. Breuer, Sandeep K. Gupta, Shahin Nazarian: Theory of redundancy for logic circuits to maximize yield/area. ISQED 2012: 663-671 |
| c106 | | Mohammad Mirza-Aghatabar, Melvin A. Breuer, Sandeep K. Gupta: A design flow to maximize yield/area of physical devices via redundancy. ITC 2012: 1-10 |
| 2011 | ||
| c105 | | Jae Chul Cha, Sandeep K. Gupta: Yield-per-Area Optimization for 6T-SRAMs Using an Integrated Approach to Exploit Spares and ECC to Efficiently Combat High Defect and Soft-Error Rates. Asian Test Symposium 2011: 126-135 |
| c104 | | Prasanjeet Das, Sandeep K. Gupta: On Generating Vectors for Accurate Post-Silicon Delay Characterization. Asian Test Symposium 2011: 251-260 |
| c103 | | Doochul Shin, Sandeep K. Gupta: A new circuit simplification method for error tolerant applications. DATE 2011: 1566-1571 |
| c102 | | |
| c101 | | Sandeep K. Gupta, ShubhLakshmi Agrwal, Yogesh K. Meena, Neeta Nain: A Hybrid Method of Feature Extraction for Facial Expression Recognition. SITIS 2011: 422-425 |
| 2010 | ||
| j33 | | Shamim Begum, Ahmed Helmy, Sandeep K. Gupta: Modeling the interactions between MAC and higher layer: A systematic approach to generate high-level scenarios from MAC-layer scenarios. ACM Trans. Model. Comput. Simul. 21(1): 7 (2010) |
| c100 | | Mohammad Mirza-Aghatabar, Melvin A. Breuer, Sandeep K. Gupta: HYPER: A Heuristic for Yield/Area imProvEment Using Redundancy in SoC. Asian Test Symposium 2010: 249-254 |
| c99 | | Doochul Shin, Sandeep K. Gupta: Approximate logic synthesis for error tolerant applications. DATE 2010: 957-960 |
| c98 | | Mohammad Mirza-Aghatabar, Melvin A. Breuer, Sandeep K. Gupta: Algorithms to maximize yield and enhance yield/area of pipeline circuitry by insertion of switches and redundant modules. DATE 2010: 1249-1254 |
| c97 | | Kun Young Chung, Sandeep K. Gupta: Design and test of latch-based circuits to maximize performance, yield, and delay test quality. ITC 2010: 94-103 |
| 2009 | ||
| j32 | | Carlos de M. Cordeiro, Romano Fantacci, Sandeep K. Gupta, Joseph A. Paradiso, Asim Smailagic, Mani B. Srivastava: Body Area Networking: Technology and Applications. IEEE Journal on Selected Areas in Communications 27(1): 1-4 (2009) |
| j31 | | Zhigang Jiang, Sandeep K. Gupta: Threshold Testing: Improving Yield for Nanoscale VLSI. IEEE Trans. on CAD of Integrated Circuits and Systems 28(12): 1883-1895 (2009) |
| c96 | | Mohammad Mirza-Aghatabar, Melvin A. Breuer, Sandeep K. Gupta: SIRUP: Switch Insertion in RedUndant Pipeline Structures for Yield and Yield/Area Improvement. Asian Test Symposium 2009: 193-199 |
| c95 | | Tong-Yu Hsieh, Melvin A. Breuer, Murali Annavaram, Sandeep K. Gupta, Kuen-Jong Lee: Tolerance of performance degrading faults for effective yield improvement. ITC 2009: 1-10 |
| c94 | | Shamim Begum, Ahmed Helmy, Sandeep K. Gupta: Modeling and test generation for worst-case performance evaluation of MAC protocols for wireless ad hoc networks. MASCOTS 2009: 1-10 |
| c93 | | Kun Young Chung, Sandeep K. Gupta: Efficient Scheduling of Path Delay Tests for Latch-Based Circuits. VTS 2009: 103-110 |
| 2008 | ||
| j30 | | Jung-Yup Kang, Sandeep K. Gupta, Jean-Luc Gaudiot: An Efficient Data-Distribution Mechanism in a Processor-In-Memory (PIM) Architecture Applied to Motion Estimation. IEEE Trans. Computers 57(3): 375-388 (2008) |
| c92 | | Jae Chul Cha, Sandeep K. Gupta: Matrix Inversion on a PIM (Processor-in-Memory). CSSE (3) 2008: 419-422 |
| c91 | | Jae Chul Cha, Sandeep K. Gupta: Characterization of granularity and redundancy for SRAMs for optimal yield-per-area. ICCD 2008: 219-226 |
| c90 | | Jae Chul Cha, Sandeep K. Gupta: Data Partitioning and Placement Schemes for Matrix Multiplications on a PIM Architecture. ISPDC 2008: 309-316 |
| c89 | | I-De Huang, Yi-Shing Chang, Suriyaprakash Natarajan, Ramesh Sharma, Sandeep K. Gupta: On Accelerating Path Delay Fault Simulation of Long Test Sequences. ITC 2008: 1-9 |
| c88 | | I-De Huang, Yi-Shing Chang, Sandeep K. Gupta, Sreejit Chakravarty: An Industrial Case Study of Sticky Path-Delay Faults. VTS 2008: 395-402 |
| 2007 | ||
| c87 | | Hugo Cheung, Sandeep K. Gupta: Accurate modeling and fault simulation of Byzantine resistive bridges. ICCD 2007: 347-353 |
| c86 | | |
| c85 | | Shamim Begum, Sandeep K. Gupta, Ahmed Helmy: Performance Analysis of Wireless MAC Protocols Using a Search Based Framework. MASCOTS 2007: 95-102 |
| 2006 | ||
| j29 | | Seongmoon Wang, Sandeep K. Gupta: LT-RTPG: a new test-per-scan BIST TPG for low switching activity. IEEE Trans. on CAD of Integrated Circuits and Systems 25(8): 1565-1574 (2006) |
| c84 | | Shahin Nazarian, Massoud Pedram, Sandeep K. Gupta, Melvin A. Breuer: STAX: statistical crosstalk target set compaction. DATE Designers' Forum 2006: 172-177 |
| c83 | | Shideh Shahidi, Sandeep K. Gupta: Estimating Error Rate during Self-Test via One's Counting. ITC 2006: 1-9 |
| c82 | | Kun Young Chung, Sandeep K. Gupta: Low-Cost Scan-Based Delay Testing of Latch-Based Circuits with Time Borrowing. VTS 2006: 8-15 |
| 2005 | ||
| j28 | | Ahmed Helmy, Sandeep K. Gupta: FOTG: fault-oriented stress testing of IP multicast. IEEE Communications Letters 9(4): 375-377 (2005) |
| c81 | | Wichian Sirisaengtaksin, Sandeep K. Gupta: A Methodology to Compute Bounds on Crosstalk Effects in Arbitrary Interconnects. Asian Test Symposium 2005: 112-119 |
| c80 | | I-De Huang, Sandeep K. Gupta: Selection of Paths for Delay Testing. Asian Test Symposium 2005: 208-215 |
| c79 | | Zhigang Jiang, Sandeep K. Gupta: Threshold testing: Covering bridging and other realistic faults. Asian Test Symposium 2005: 390-397 |
| c78 | | S. Ebrahimi-Taghizadeh, Ahmed Helmy, Sandeep K. Gupta: TCP vs. TCP: a systematic study of adverse impact of short-lived TCP flows on long-lived TCP flows. INFOCOM 2005: 926-937 |
| c77 | | Shahdad Irajpour, Sandeep K. Gupta, Melvin A. Breuer: Multiple tests for each gate delay fault: higher coverage and lower test application cost. ITC 2005: 9 |
| 2004 | ||
| j27 | | Melvin A. Breuer, Sandeep K. Gupta, T. M. Mak: Defect and Error Tolerance in the Presence of Massive Numbers of Defects. IEEE Design & Test of Computers 21(3): 216-227 (2004) |
| j26 | | Karim Seada, Ahmed Helmy, Sandeep K. Gupta: A framework for systematic evaluation of multicast congestion control protocols. IEEE Journal on Selected Areas in Communications 22(10): 2048-2061 (2004) |
| j25 | | Ahmed Helmy, Sandeep K. Gupta, Deborah Estrin: The STRESS method for boundary-point performance analysis of end-to-end multicast timer-suppression mechanisms. IEEE/ACM Trans. Netw. 12(1): 44-58 (2004) |
| c76 | | Melvin A. Breuer, Sandeep K. Gupta, Shahin Nazarian: Efficient Identification of Crosstalk Induced Slowdown Targets. Asian Test Symposium 2004: 124-131 |
| c75 | | Wichian Sirisaengtaksin, Sandeep K. Gupta: Modeling and Testing Crosstalk Faults in Inter-Core Interconnects that Include Tri-State and Bi-Directional Nets. Asian Test Symposium 2004: 132-139 |
| c74 | | Lei Wang, Sandeep K. Gupta, Melvin A. Breuer: Modeling and Simulation for Crosstalk Aggravated by Weak-Bridge Defects between On-Chip Interconnects. Asian Test Symposium 2004: 440-447 |
| c73 | | Shahdad Irajpour, Sandeep K. Gupta, Melvin A. Breuer: Timing-Independent Testing of Crosstalk in the Presence of Delay Producing Defects Using Surrogate Fault Models. ITC 2004: 1024-1033 |
| c72 | | Md. Saffat Quasem, Sandeep K. Gupta: Designing Reconfigurable Multiple Scan Chains for Systems-on-Chip. VTS 2004: 367-376 |
| 2003 | ||
| j24 | | Md. Saffat Quasem, Zhigang Jiang, Sandeep K. Gupta: Benefits of a SoC-Specific Test Methodology. IEEE Design & Test of Computers 20(3): 68-77 (2003) |
| c71 | | Arani Sinha, Sandeep K. Gupta, Melvin A. Breuer: An Enhanced Test Generator for Capacitance Induced Crosstalk Delay Faults. Asian Test Symposium 2003: 174-177 |
| c70 | | Zhigang Jiang, Sandeep K. Gupta: A Test Generation Approach for Systems-on-Chip that Use Intellectual Property Cores. Asian Test Symposium 2003: 278-283 |
| c69 | | Md. Saffat Quasem, Sandeep K. Gupta: Designing Multiple Scan Chains for Systems-on-Chip. Asian Test Symposium 2003: 424-427 |
| c68 | | Kun Young Chung, Sandeep K. Gupta: Structural Delay Testing of Latch-based High-speed Pipelines with Time Borrowing. ITC 2003: 1089-1097 |
| c67 | | Yi-Shing Chang, Sandeep K. Gupta, Melvin A. Breuer: Test Generation for Maximizing Ground Bounce Considering Circuit Delay. VTS 2003: 151-157 |
| c66 | | Nabil M. Abdulrazzaq, Sandeep K. Gupta: Path-Delay Fault Simulation for Circuits with Large Numbers of Paths for Very Large Test Sets. VTS 2003: 186-196 |
| c65 | | Sultan M. Al-Harbi, Sandeep K. Gupta: Generating Complete and Optimal March Tests for Linked Faults in Memories. VTS 2003: 254-266 |
| c64 | | Shahdad Irajpour, Shahin Nazarian, Lei Wang, Sandeep K. Gupta, Melvin A. Breuer: Analyzing Crosstalk in the Presence of Weak Bridge Defects. VTS 2003: 385-392 |
| 2002 | ||
| j23 | | Wei-Yu Chen, Sandeep K. Gupta, Melvin A. Breuer: Test Generation for Crosstalk-Induced Faults: Framework and Computational Results. J. Electronic Testing 18(1): 17-28 (2002) |
| j22 | | Liang-Chi Chen, Sandeep K. Gupta, Melvin A. Breuer: TA-PSV - Timing Analysis for Partially Specified Vectors. J. Electronic Testing 18(1): 73-88 (2002) |
| j21 | | Seongmoon Wang, Sandeep K. Gupta: DS-LFSR: a BIST TPG for low switching activity. IEEE Trans. on CAD of Integrated Circuits and Systems 21(7): 842-851 (2002) |
| j20 | | Seongmoon Wang, Sandeep K. Gupta: An automatic test pattern generator for minimizing switching activity during scan testing activity. IEEE Trans. on CAD of Integrated Circuits and Systems 21(8): 954-968 (2002) |
| j19 | | Wei-Yu Chen, Sandeep K. Gupta, Melvin A. Breuer: Analytical models for crosstalk excitation and propagation in VLSI circuits. IEEE Trans. on CAD of Integrated Circuits and Systems 21(10): 1117-1131 (2002) |
| c63 | | Wichian Sirisaengtaksin, Sandeep K. Gupta: Enhanced Crosstalk Fault Model and Methodology to Generate Tests for Arbitrary Inter-core Interconnect Topology. Asian Test Symposium 2002: 163-169 |
| c62 | | I-De Huang, Sandeep K. Gupta, Melvin A. Breuer: Accurate and Efficient Static Timing Analysis with Crosstalk. ICCD 2002: 265-272 |
| c61 | | Shahin Nazarian, Hang Huang, Suriyaprakash Natarajan, Sandeep K. Gupta, Melvin A. Breuer: XIDEN: Crosstalk Target Identification Framework. ITC 2002: 365-374 |
| c60 | | Zhigang Jiang, Sandeep K. Gupta: An ATPG for Threshold Testing: Obtaining Acceptable Yield in Future Processes. ITC 2002: 824-833 |
| i3 | | Ahmed Helmy, Sandeep K. Gupta, Deborah Estrin: The STRESS Method for Boundary-point Performance Analysis of End-to-end Multicast Timer-Suppression Mechanisms. CoRR cs.NI/0208023 (2002) |
| 2001 | ||
| j18 | | Pankaj Pant, Yuan-Chieh Hsu, Sandeep K. Gupta, Abhijit Chatterjee: Path delay fault diagnosis in combinational circuits with implicitfault enumeration. IEEE Trans. on CAD of Integrated Circuits and Systems 20(10): 1226-1235 (2001) |
| j17 | | Ishwar Parulkar, Sandeep K. Gupta, Melvin A. Breuer: Introducing redundant computations in RTL data paths for reducing BIST resources. ACM Trans. Design Autom. Electr. Syst. 6(3): 423-445 (2001) |
| c59 | | Liang-Chi Chen, Sandeep K. Gupta, Melvin A. Breuer: A New Gate Delay Model for Simultaneous Switching and Its Applications. DAC 2001: 289-294 |
| c58 | | Md. Saffat Quasem, Sandeep K. Gupta: Exact fault simulation for systems on Silicon that protects each core's intellectual property. DATE 2001: 804 |
| c57 | | Suriyaprakash Natarajan, Sandeep K. Gupta, Melvin A. Breuer: Switch-level delay test of domino logic circuits. ITC 2001: 367-376 |
| c56 | | Liang-Chi Chen, T. M. Mak, Sandeep K. Gupta, Melvin A. Breuer: Crosstalk test generation on pseudo industrial circuits: a case study. ITC 2001: 548-557 |
| c55 | | Sultan M. Al-Harbi, Sandeep K. Gupta: An Efficient Methodology for Generating Optimal and Uniform March Tests. VTS 2001: 231-239 |
| c54 | | Yi-Shing Chang, Sandeep K. Gupta, Melvin A. Breuer: Test Generation for Maximizing Ground Bounce for Internal Circuitry with Reconvergent Fan-out. VTS 2001: 358-367 |
| 2000 | ||
| j16 | | Chen-Huan Chiang, Sandeep K. Gupta: BIST TPG for Combinational Cluster Interconnect Testing at Board Level. J. Electronic Testing 16(5): 427-442 (2000) |
| j15 | | Rajagopalan Srinivasan, Sandeep K. Gupta, Melvin A. Breuer: Novel Test Pattern Generators for Pseudoexhaustive Testing. IEEE Trans. Computers 49(11): 1228-1240 (2000) |
| c53 | | Chen-Huan Chiang, Sandeep K. Gupta: BIST TPG for SRAM cluster interconnect testing at board level. Asian Test Symposium 2000: 58-65 |
| c52 | | Liang-Chi Chen, Sandeep K. Gupta, Melvin A. Breuer: A new framework for static timing analysis, incremental timing refinement, and timing simulation. Asian Test Symposium 2000: 102-107 |
| c51 | | Wei-Yu Chen, Sandeep K. Gupta, Melvin A. Breuer: Test generation for crosstalk-induced faults: framework and computational result. Asian Test Symposium 2000: 305-310 |
| c50 |  | Ahmed Helmy, Sandeep K. Gupta, Deborah Estrin, Alberto Cerpa, Yan Yu: Systematic Performance Evaluation of Multipoint Protocols. FORTE 2000: 189-204 |
| c49 | | Sandeep K. Gupta, Wang-Chien Lee, Pradip K. Srimani: Message from the Chairs. ICPP Workshops 2000: 3 |
| c48 | | Nabil M. Abdulrazzaq, Sandeep K. Gupta: Test generation for path-delay faults in one-dimensional iterative logic arrays. ITC 2000: 326-335 |
| c47 | | Shamim Begum, Meeta Sharma, Ahmed Helmy, Sandeep K. Gupta: Systematic Testing of Protocol Robustness: Case Studies on Mobile IP and MARS. LCN 2000: 369-380 |
| c46 | | Melvin A. Breuer, Sandeep K. Gupta: New Validation and Test Problems for High Performance Deep Submicron VLSI Circuits. VLSI Design 2000: 8 |
| c45 | | Hugo Cheung, Sandeep K. Gupta: A Framework to Minimize Test Escape and Yield Loss during IDDQ Testing: A Case Study. VTS 2000: 89-96 |
| i2 | | Ahmed Helmy, Sandeep K. Gupta, Deborah Estrin, Alberto Cerpa, Yan Yu: Systematic Performance Evaluation of Multipoint Protocols. CoRR cs.NI/0006029 (2000) |
| i1 | | Ahmed Helmy, Deborah Estrin, Sandeep K. Gupta: Systematic Testing of Multicast Routing Protocols: Analysis of Forward and Backward Search Techniques. CoRR cs.NI/0007005 (2000) |
| 1999 | ||
| c44 | | Arani Sinha, Sandeep K. Gupta, Melvin A. Breuer: Validation and test generation for oscillatory noise in VLSI interconnects. ICCAD 1999: 289-296 |
| c43 | | Seongmoon Wang, Sandeep K. Gupta: LT-RTPG: a new test-per-scan BIST TPG for low heat dissipation. ITC 1999: 85-94 |
| c42 | | Suriyaprakash Natarajan, Sandeep K. Gupta, Melvin A. Breuer: Switch-level delay test. ITC 1999: 171-180 |
| c41 | | Wei-Yu Chen, Sandeep K. Gupta, Melvin A. Breuer: Test generation for crosstalk-induced delay in integrated circuits. ITC 1999: 191-200 |
| c40 | | Yi-Shing Chang, Sandeep K. Gupta, Melvin A. Breuer: Test Generation for Ground Bounce in Internal Logic Circuitry. VTS 1999: 95-105 |
| 1998 | ||
| j14 | | Ishwar Parulkar, Sandeep K. Gupta, Melvin A. Breuer: Allocation Techniques for Reducing BIST Area Overhead of Data Paths. J. Electronic Testing 13(2): 149-166 (1998) |
| j13 | | Ishwar Parulkar, Sandeep K. Gupta, Melvin A. Breuer: Estimation of BIST Resources During High-Level Synthesis. J. Electronic Testing 13(3): 221-237 (1998) |
| j12 | | Seongmoon Wang, Sandeep K. Gupta: ATPG for Heat Dissipation Minimization During Test Application. IEEE Trans. Computers 47(2): 256-262 (1998) |
| j11 | | Chih-Ang Chen, Sandeep K. Gupta: Efficient BIST TPG design and test set compaction via input reduction. IEEE Trans. on CAD of Integrated Circuits and Systems 17(8): 692-705 (1998) |
| j10 | | Rajagopalan Srinivasan, Sandeep K. Gupta, Melvin A. Breuer: Bounds on pseudoexhaustive test lengths. IEEE Trans. VLSI Syst. 6(3): 420-431 (1998) |
| c39 | | Yuan-Chieh Hsu, Sandeep K. Gupta: An Automatic Test Pattern Generator for At-Speed Robust Path Delay Testing. Asian Test Symposium 1998: 88-95 |
| c38 | | Chen-Huan Chiang, Sandeep K. Gupta: BIST TPG for Combinational Cluster (Glue Logic) Interconnect Testing at Board Level. Asian Test Symposium 1998: 244-252 |
| c37 | | Ishwar Parulkar, Sandeep K. Gupta, Melvin A. Breuer: Introducing Redundant Computations in a Behavior for Reducing BIST Resources. DAC 1998: 548-553 |
| c36 | | Ishwar Parulkar, Sandeep K. Gupta, Melvin A. Breuer: Scheduling and Module Assignment for Reducing Bist Resources. DATE 1998: 66-73 |
| c35 | | Suriyaprakash Natarajan, Melvin A. Breuer, Sandeep K. Gupta: Process Variations and their Impact on Circuit Operation. DFT 1998: 73- |
| c34 | | Ahmed Helmy, Deborah Estrin, Sandeep K. Gupta: Fault-oriented Test Generation for Multicast Routing Protocol Design. FORTE 1998: 93-109 |
| c33 | | Weiyu Chen, Sandeep K. Gupta, Melvin A. Breuer: Test generation in VLSI circuits for crosstalk noise. ITC 1998: 641-650 |
| c32 | | Yuan-Chieh Hsu, Sandeep K. Gupta: A new path-oriented effect-cause methodology to diagnose delay failures. ITC 1998: 758-767 |
| c31 | | Sultan M. Al-Harbi, Sandeep K. Gupta: A Methodology for Transforming Memory Tests for In-System Testing of Direct Mapped Cache Tags. VTS 1998: 394-400 |
| 1997 | ||
| c30 | | Seongmoon Wang, Sandeep K. Gupta: ATPG for Heat Dissipation Minimization During Scan Testing. DAC 1997: 614-619 |
| c29 | | |
| c28 | | Weiyu Chen, Melvin A. Breuer, Sandeep K. Gupta: Analytic Models for Crosstalk Delay and Pulse Analysis Under Non-Ideal Inputs. ITC 1997: 809-818 |
| c27 | | Seongmoon Wang, Sandeep K. Gupta: DS-LFSR: A New BIST TPG for Low Heat Dissipation. ITC 1997: 848-857 |
| c26 | | Liang-Chi Chen, Sandeep K. Gupta, Melvin A. Breuer: High Quality Robust Tests for Path Delay Faults. VTS 1997: 88-93 |
| c25 | | Yi-Shing Chang, Sandeep K. Gupta, Melvin A. Breuer: Analysis of Ground Bounce in Deep Sub-Micron Circuits. VTS 1997: 110-116 |
| c24 | | Chen-Huan Chiang, Sandeep K. Gupta: BIST TPGs for Faults in Board Level Interconnect via Boundary Scan. VTS 1997: 376-383 |
| 1996 | ||
| j9 | | Sandeep K. Gupta, Dhiraj K. Pradhan: Utilization of On-Line (Concurrent) Checkers During Built-In-Self-Test and Vice Versa. IEEE Trans. Computers 45(1): 63-73 (1996) |
| j8 | | Chih-Ang Chen, Sandeep K. Gupta: BIST Test Pattern Generators for Two-Pattern Testing-Theory and Design Algorithms. IEEE Trans. Computers 45(3): 257-269 (1996) |
| j7 | | Yuan-Chieh Hsu, Sandeep K. Gupta: A Simulator for At-Speed Robust Testing of Path Delay Faults in Combinational Circuits. IEEE Trans. Computers 45(11): 1312-1318 (1996) |
| j6 | | Chih-Ang Chen, Sandeep K. Gupta: Design of efficient BIST test pattern generators for delay testing. IEEE Trans. on CAD of Integrated Circuits and Systems 15(12): 1568-1575 (1996) |
| c23 | | Ishwar Parulkar, Sandeep K. Gupta, Melvin A. Breuer: Lower Bounds on Test Resources for Scheduled Data Flow Graphs. DAC 1996: 143-148 |
| c22 | | Chih-Ang Chen, Sandeep K. Gupta: A Satisfiability-Based Test Generator for Path Delay Faults in Combinational Circuts. DAC 1996: 209-214 |
| c21 | | Zhiyong Li, John H. Reif, Sandeep K. Gupta: Synthesizing Efficient Out-of-Core Programs for Block Recursive Algorithms Using Block-Cyclic Data Distributions. ICPP, Vol. 2 1996: 142-149 |
| c20 | | Hugo Cheung, Sandeep K. Gupta: A BIST Methodology for Comprehensive Testing of RAM with Reduced Heat Dissipation. ITC 1996: 386-395 |
| c19 | | Melvin A. Breuer, Sandeep K. Gupta: Process-Aggravated Noise (PAN): New Validation and Test Problems. ITC 1996: 914-923 |
| c18 | | Sandeep K. Gupta, Slawomir Pilarski, Sudhakar M. Reddy, Jacob Savir, Prab Varma: Delay Fault Testing: How Robust are Our Models? VTS 1996: 502-503 |
| 1995 | ||
| j5 | | Sandeep K. Gupta, John D. Kececioglu, Alejandro A. Schäffer: Improving the Practical Space and Time Efficiency of the Shortest-Paths Approach to Sum-of-Pairs Multiple Sequence Alignment. Journal of Computational Biology 2(3): 459-472 (1995) |
| j4 | | Mody Lempel, Sandeep K. Gupta: Zero Aliasing for Modeled Faults. IEEE Trans. Computers 44(11): 1283-1295 (1995) |
| j3 | | Mody Lempel, Sandeep K. Gupta, Melvin A. Breuer: Test embedding with discrete logarithms. IEEE Trans. on CAD of Integrated Circuits and Systems 14(5): 554-566 (1995) |
| c17 | | Sandeep K. Gupta, John D. Kececioglu, Alejandro A. Schäffer: Making the Shortest-Paths Approach to Sum-of-Pairs Multiple Sequence Alignment More Space Efficient in Practice (Extended Abstract). CPM 1995: 128-143 |
| c16 | | Ishwar Parulkar, Sandeep K. Gupta, Melvin A. Breuer: Data Path Allocation for Synthesizing RTL Designs with Low BIST Area Overhead. DAC 1995: 395-401 |
| c15 | | Chih-Ang Chen, Sandeep K. Gupta: A Methodology to Design Efficient BIST Test Pattern Generators. ITC 1995: 814-823 |
| 1994 | ||
| c14 | | Wen-Chang Fang, Sandeep K. Gupta: Clock Grouping: A Low Cost DFT Methodology for Delay Testing. DAC 1994: 94-99 |
| c13 | | Sen-Pin Lin, Sandeep K. Gupta, Melvin A. Breuer: A Low Cost BIST Methodology and Associated Novel Test Pattern Generator. EDAC-ETC-EUROASIC 1994: 106-112 |
| c12 | | Chih-Ang Chen, Sandeep K. Gupta: BIST Test Pattern Generators for Stuck-Open and Delay Testing. EDAC-ETC-EUROASIC 1994: 289-296 |
| c11 | | |
| c10 | | Seongmoon Wang, Sandeep K. Gupta: ATPG for Heat Dissipation Minimization During Test Application. ITC 1994: 250-258 |
| c9 | | Mody Lempel, Sandeep K. Gupta, Melvin A. Breuer: Test embedding with discrete logarithms. VTS 1994: 74-80 |
| c8 | | Weili Wang, Sandeep K. Gupta: Weighted random robust path delay testing of synthesized multilevel circuits. VTS 1994: 291-297 |
| 1993 | ||
| c7 | | Rajagopalan Srinivasan, Sandeep K. Gupta, Melvin A. Breuer: An Efficient Partitioning Strategy for Pseudo-Exhaustive Testing. DAC 1993: 242-248 |
| c6 | | Rajagopalan Srinivasan, Sandeep K. Gupta, Melvin A. Breuer: Novel Test Pattern Generators for Pseudo-Exhaustive Testing. ITC 1993: 1041-1050 |
| 1992 | ||
| c5 | | |
| 1991 | ||
| j2 | | Dhiraj K. Pradhan, Sandeep K. Gupta: A New Framework for Designing and Analyzing BIST Techniques and Zero Aliasing Compression. IEEE Trans. Computers 40(6): 743-763 (1991) |
| c4 | | Mark G. Karpovsky, Sandeep K. Gupta, Dhiraj K. Pradhan: Aliasing and Diagnosis Probability in MISR and STUMPS Using a General Error Model. ITC 1991: 828-839 |
| 1990 | ||
| j1 | | Dhiraj K. Pradhan, Sandeep K. Gupta, Mark G. Karpovsky: Aliasing Probability for Multiple Input Signature Analyzer. IEEE Trans. Computers 39(4): 586-591 (1990) |
| c3 | | Sandeep K. Gupta, Dhiraj K. Pradhan, Sudhakar M. Reddy: Zero aliasing compression. FTCS 1990: 254-263 |
| 1988 | ||
| c2 | | Sandeep K. Gupta, Dhiraj K. Pradhan: A New Framework for Designing and Analyzing BIST Techniques: Computation of Exact Aliasing Probability. ITC 1988: 329-342 |
| c1 | | Sandeep K. Gupta, Melvin A. Breuer, Jung-Cheun Lien: Concurrent Control of Multiple BIT Structures. ITC 1988: 431-442 |
Colors in the list of coauthors
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