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Michael Hübner
2010 – today
- 2013
[j17]Nikolaos S. Voros, Michael Hübner, Jürgen Becker, Matthias Kühnle, Florian Thoma, Arnaud Grasset, Paul Brelet, Philippe Bonnot, Fabio Campi, Eberhard Schüler, Henning Sahlbach, Sean Whitty, Rolf Ernst, Enrico Billich, Claudia Tischendorf, Ulrich Heinkel, Frank Ieromnimon, Dimitrios Kritharidis, Axel Schneider, Joachim Knäblein, Wolfram Putzke-Röming: MORPHEUS: A heterogeneous dynamically reconfigurable platform for designing highly complex embedded systems. ACM Trans. Embedded Comput. Syst. 12(3): 70 (2013)- 2012
- [j16]Diana Göhringer, Lukas Meder, Stephan Werner, Oliver Oey, Jürgen Becker, Michael Hübner: Adaptive Multiclient Network-on-Chip Memory Core: Hardware Architecture, Software Abstraction Layer, and Application Exploration. Int. J. Reconfig. Comp. 2012 (2012)
- [j15]
- [c94]Ali Azarian, João Canas Ferreira, Stephan Werner, Zlatko Petrov, João M. P. Cardoso, Michael Hübner: Analysis of error detection schemes: Toolchain support and hardware/software implications. AHS 2012: 62-69
- [c93]Jörg Henkel, Andreas Herkersdorf, Lars Bauer, Thomas Wild, Michael Hübner, Ravi Kumar Pujari, Artjom Grudnitsky, Jan Heisswolf, Aurang Zaib, Benjamin Vogel, Vahid Lari, Sebastian Kobbe: Invasive manycore architectures. ASP-DAC 2012: 193-200
- [c92]Max Ferger, Muhammed Al Kadi, Michael Hübner, Martijn Koedam, Shubhendu Sinha, Kees Goossens, Gabriel Marchesan Almeida, José Rodrigo Azambuja, Jürgen Becker: Hardware / Software Virtualization for the Reconfigurable Multicore Platform. CSE 2012: 341-344
- [c91]Oliver Oey, Stephan Werner, Diana Göhringer, Andreas Stuckert, Jürgen Becker, Michael Hübner: Virtualization of heterogeneous and adaptive multi-core/multi-board systems. DASIP 2012: 1-2
- [c90]Stephan Werner, Oliver Oey, Diana Göhringer, Michael Hübner, Jürgen Becker: Virtualized on-chip distributed computing for heterogeneous reconfigurable multi-core systems. DATE 2012: 280-283
- [c89]Jürgen Becker, Timo Stripf, Oliver Oey, Michael Hübner, Steven Derrien, Daniel Menard, Olivier Sentieys, Gerard K. Rauwerda, Kim Sunesen, Nikolaos Kavvadias, Kostas Masselos, George Goulas, Panayiotis Alefragis, Nikolaos S. Voros, Dimitrios Kritharidis, Nikolaos Mitas, Diana Göhringer: From Scilab to High Performance Embedded Multicore Systems: The ALMA Approach. DSD 2012: 114-121
- [c88]Jürgen Becker, Jinian Bian, Christophe Bobda, René Cumplido, Michael Hübner: RAW Introduction. IPDPS Workshops 2012: 208-212
- [c87]Harry Sidiropoulos, Kostas Siozios, Peter Figuli, Dimitrios Soudris, Michael Hübner: On Supporting Efficient Partial Reconfiguration with Just-In-Time Compilation. IPDPS Workshops 2012: 328-335
- [c86]Carsten Tradowsky, Florian Thoma, Michael Hübner, Jürgen Becker: On Dynamic Run-time Processor Pipeline Reconfiguration. IPDPS Workshops 2012: 419-424
- [c85]Carsten Tradowsky, Enrique Cordero, Thorsten Deuser, Michael Hübner, Jürgen Becker: Determination of on-chip temperature gradients on reconfigurable hardware. ReConFig 2012: 1-8
- [c84]Diana Göhringer, Mounir Chemaou, Michael Hübner: Invited paper: On-chip monitoring for adaptive heterogeneous multicore systems. ReCoSoC 2012: 1-7
- [c83]Timo Stripf, Oliver Oey, Thomas Bruckschlögl, Ralf König, Michael Hübner, Jürgen Becker, Gerard K. Rauwerda, Kim Sunesen, Nikolaos Kavvadias, Grigoris Dimitroulakos, Kostas Masselos, Dimitrios Kritharidis, Nikolaos Mitas, George Goulas, Panayiotis Alefragis, Nikolaos S. Voros, Steven Derrien, Daniel Menard, Olivier Sentieys, Diana Göhringer, Thomas Perschke: A flexible approach for compiling scilab to reconfigurable multi-core embedded systems. ReCoSoC 2012: 1-8
- [c82]Fabrice Lemonnier, Philippe Millet, Gabriel Marchesan Almeida, Michael Hübner, Jürgen Becker, Sébastien Pillement, Olivier Sentieys, Martijn Koedam, Shubhendu Sinha, Kees Goossens, Christian Piguet, Marc-Nicolas Morgan, Romain Lemaire: Towards future adaptive multiprocessor systems-on-chip: An innovative approach for flexible architectures. ICSAMOS 2012: 228-235
- [c81]Michael Hübner, Diana Göhringer, Carsten Tradowsky, Jörg Henkel, Jürgen Becker: Adaptive processor architecture - invited paper. ICSAMOS 2012: 244-251
- [c80]George Goulas, Panayiotis Alefragis, Nikolaos S. Voros, Christos Valouxis, Christos Gogos, Nikolaos Kavvadias, Grigoris Dimitroulakos, Kostas Masselos, Diana Göhringer, Steven Derrien, Daniel Menard, Olivier Sentieys, Michael Hübner, Timo Stripf, Oliver Oey, Jürgen Becker, Gerard K. Rauwerda, Kim Sunesen, Dimitrios Kritharidis, Nikolaos Mitas: From Scilab to multicore embedded systems: Algorithms and methodologies. ICSAMOS 2012: 268-275
- [c79]Carsten Tradowsky, Florian Thoma, Michael Hübner, Jürgen Becker: LISPARC: Using an architecture description language approach for modelling an adaptive processor microarchitecture. SIES 2012: 279-282
- [i1]David Hillerkuss, Rene Schmogrow, Matthias Meyer, Stefan Wolf, Meinert Jordan, Philipp Kleinow, Nicole Lindenmann, Philipp C. Schindler, Argishti Melikyan, Xin Yang, Shalva Ben-Ezra, Bernd Nebendahl, Michael Dreschmann, Joachim Meyer, Francesca Parmigiani, Periklis Petropoulos, Bojan Resan, Aandreas Oehler, Kurt Weingarten, Lars Altenhain, Tobias Ellermeyer, Matthias Moeller, Michael Hübner, Jürgen Becker, Christian Koos, Wolfgang Freude, Juerg Leuthold: Single-laser 32.5 Tbit/s Nyquist WDM transmission. CoRR abs/1203.2516 (2012)
- 2011
- [e2]Michael Hübner, Jürgen Becker (Eds.): Multiprocessor System-on-Chip - Hardware Design and Tool Integration. Springer 2011, ISBN 978-1-4419-6459-5
- [j14]Arnaud Grasset, Philippe Millet, Philippe Bonnot, Sami Yehia, Wolfram Putzke-Röming, Fabio Campi, Alberto Rosti, Michael Hübner, Nikolaos S. Voros, Davide Rossi, Henning Sahlbach, Rolf Ernst: The MORPHEUS Heterogeneous Dynamically Reconfigurable Platform. International Journal of Parallel Programming 39(3): 328-356 (2011)
- [j13]Matthias Birk, Clemens Hagner, Matthias Balzer, Nicole V. Ruiter, Michael Hübner, Jürgen Becker: Evaluation of the Reconfiguration of the Data Acquisition System for 3D USCT. Int. J. Reconfig. Comp. 2011 (2011)
- [j12]Diana Göhringer, Michael Hübner, Etienne Nguepi Zeutebouo, Jürgen Becker: Operating System for Runtime Reconfigurable Multiprocessor Systems. Int. J. Reconfig. Comp. 2011 (2011)
- [j11]Diana Göhringer, Jonathan Obie, André L. S. Braga, Michael Hübner, Carlos Humberto Llanos Quintero, Jürgen Becker: Exploration of the Power-Performance Tradeoff through Parameterization of FPGA-Based Multiprocessor Systems. Int. J. Reconfig. Comp. 2011 (2011)
- [j10]Michael Hübner, Jürgen Becker, Loïc Lagadec, Gilles Sassatelli: Selected Papers from the International Workshop on Reconfigurable Communication-Centric Systems on Chips (ReCoSoC' 2010). Int. J. Reconfig. Comp. 2011 (2011)
- [p2]Diana Göhringer, Michael Hübner, Jürgen Becker: Adaptive Multiprocessor System-on-Chip Architecture: New Degrees of Freedom in System Design and Runtime Support. Multiprocessor System-on-Chip 2011: 127-151
- [c78]Monica Magalhães Pereira, Lars Braun, Michael Hübner, Jürgen Becker, Luigi Carro: Run-time resource instantiation for fault tolerance in FPGAs. AHS 2011: 88-95
- [c77]Peter Figuli, Michael Hübner, Romuald Girardey, Falco Bapp, Thomas Bruckschlögl, Florian Thoma, Jörg Henkel, Jürgen Becker: A heterogeneous SoC architecture with embedded virtual FPGA cores and runtime Core Fusion. AHS 2011: 96-103
- [c76]Matthias Birk, Alexander Guth, Michael Zapf, Matthias Balzer, Nicole V. Ruiter, Michael Hübner, Jürgen Becker: Acceleration of image reconstruction in 3D ultrasound computer tomography: An evaluation of CPU, GPU and FPGA computing. DASIP 2011: 67-74
- [c75]Natalie Frietsch, I. Pashkovskiy, Gert F. Trommer, Lars Braun, Matthias Birk, Michael Hübner, Jürgen Becker: Development of a method for image-based motion estimation of a VTOL-MAV on FPGA. DASIP 2011: 201-208
- [c74]Joachim Meyer, Juanjo Noguera, Michael Hübner, Lars Braun, Oliver Sander, R. M. Gil, Rodney Stewart, Jürgen Becker: Fast Start-up for Spartan-6 FPGAs using Dynamic Partial Reconfiguration. DATE 2011: 1542-1547
- [c73]Joachim Meyer, Juanjo Noguera, Michael Hübner, Rodney Stewart, Jürgen Becker: Embedded Systems Start-Up under Timing Constraints on Modern FPGAs. FPL 2011: 103-109
- [c72]Diana Göhringer, Stephan Werner, Michael Hübner, Jürgen Becker: RAMPSoCVM: Runtime Support and Hardware Virtualization for a Runtime Adaptive MPSoC. FPL 2011: 181-184
- [c71]Michael Hübner, Peter Figuli, Romuald Girardey, Dimitrios Soudris, K. Siozios, Jürgen Becker: A Heterogeneous Multicore System on Chip with Run-Time Reconfigurable Virtual FPGA Architecture. IPDPS Workshops 2011: 143-149
- [c70]Christian Schuck, Bastian Haetzer, Michael Hübner, Jürgen Becker: Online Routing of FPGA Clock Networks for Module Relocation in Partial Reconfigurable Multi Clock Designs. IPDPS Workshops 2011: 181-188
- [c69]Matthias Rümmele-Werner, Thomas Perschke, Lars Braun, Michael Hübner, Jürgen Becker: A FPGA based fast runtime reconfigurable real-time Multi-Object-Tracker. ISCAS 2011: 853-856
- [c68]Florian Thoma, Michael Hübner, Diana Göhringer, Hasam Ümitcan Yilmaz, Jürgen Becker: Power and performance optimization through MPI supported dynamic voltage and frequency scaling. MARC Symposium 2011: 75-78
- [c67]Diana Göhringer, Lukas Meder, Michael Hübner, Jürgen Becker: Adaptive Multi-client Network-on-Chip Memory. ReConFig 2011: 7-12
- [c66]Michael Hübner, Carsten Tradowsky, Diana Göhringer, Lars Braun, Florian Thoma, Jörg Henkel, Jürgen Becker: Dynamic Processor Reconfiguration. ReConFig 2011: 123-128
- [c65]Nadine Dahm, Michael Hübner, Jürgen Becker: Approach of an FPGA based adaptive stepper motor control system. ReCoSoC 2011: 1-6
- [c64]Diana Göhringer, Oliver Oey, Michael Hübner, Jürgen Becker: Heterogeneous and runtime parameterizable Star-Wheels Network-on-Chip. ICSAMOS 2011: 380-387
- [c63]José Rodrigo Azambuja, Samuel Pagliarini, Mauricio Altieri, Fernanda Lima Kastensmidt, Michael Hübner, Jürgen Becker: Using dynamic partial reconfiguration to detect sees in microprocessors through non-intrusive hybrid technique. SBCCI 2011: 161-166
- [e1]Diana Göhringer, Michael Hübner, Jürgen Becker (Eds.): 3rd Many-core Applications Research Community (MARC) Symposium. Proceedings of the 3rd MARC Symposium, Ettlingen, Germany, July 5-6, 2011. KIT Scientific Publishing, Karlsruhe 2011, ISBN 978-3-86644-717-2
- 2010
- [j9]Krzysztof Kepa, Fearghal Morgan, Krzysztof Kosciuszkiewicz, Lars Braun, Michael Hübner, Jürgen Becker: Design Assurance Strategy and Toolset for Partially Reconfigurable FPGA Systems. TRETS 4(1): 4 (2010)
- [p1]Lars Braun, Tobias Schwalb, Philipp Graf, Michael Hübner, Michael Ullmann, Klaus D. Müller-Glaser, Jürgen Becker: Adaptive Runtime System with Intelligent Allocation of Dynamically Reconfigurable Function Model and Optimized Interface Topologies. Dynamically Reconfigurable Systems 2010: 245-267
- [c62]André L. S. Braga, Carlos H. Llanos, Diana Göhringer, Jonathan Obie, Jürgen Becker, Michael Hübner: Performance, accuracy, power consumption and resource utilization analysis for hardware / software realized Artificial Neural Networks. BIC-TA 2010: 1629-1636
- [c61]Pedro C. Diniz, Marco Danelutto, Denis Barthou, Marc Gonzales, Michael Hübner: High Performance Architectures and Compilers. Euro-Par (1) 2010: 254-255
- [c60]Diana Göhringer, Michael Hübner, Michael Benz, Jürgen Becker: A Design Methodology for Application Partitioning and Architecture Development of Reconfigurable Multiprocessor Systems-on-Chip. FCCM 2010: 259-262
- [c59]Diana Göhringer, Michael Hübner, Michael Benz, Jürgen Becker: A semi-automatic toolchain for reconfigurable multiprocessor systems-on-chip: architecture development and application partitioning (abstract only). FPGA 2010: 286
- [c58]Michael Dreschmann, Michael Hübner, Moritz Roger, Oliver Sander, Christos Klamouris, Jürgen Becker, Wolfgang Freude, Juerg Leuthold: Reconfigurable Hardware for Power-over-Fiber Applications. FPL 2010: 525-531
- [c57]Andreas Kern, Christoph Schmutzler, Thilo Streichert, Michael Hübner, Jürgen Teich: Network Bandwidth Optimization of Ethernet-Based Streaming Applications in Automotive Embedded Systems. ICCCN 2010: 1-6
- [c56]Diana Göhringer, Michael Hübner, Etienne Nguepi Zeutebouo, Jürgen Becker: CAP-OS: Operating system for runtime scheduling, task mapping and resource management on reconfigurable multiprocessor architectures. IPDPS Workshops 2010: 1-8
- [c55]Michael Hübner, Diana Göhringer, Juanjo Noguera, Jürgen Becker: Fast dynamic and partial reconfiguration data path with low hardware overhead on Xilinx FPGAs. IPDPS Workshops 2010: 1-8
- [c54]Romuald Girardey, Michael Hübner, Jürgen Becker: Safety Aware Place and Route for On-Chip Redundancy in Safety Critical Applications. ISVLSI 2010: 74-79
- [c53]Michael Hübner, Joachim Meyer, Oliver Sander, Lars Braun, Jürgen Becker, Juanjo Noguera, Rodney Stewart: Fast Sequential FPGA Startup Based on Partial and Dynamic Reconfiguration. ISVLSI 2010: 190-194
- [c52]Mahtab Niknahad, Michael Hübner, Jürgen Becker: Reliability Analysis and Improvement in Nano Scale Design. ISVLSI 2010: 299-303
- [c51]Romuald Girardey, Michael Hübner, Jürgen Becker: Mixed-Signal Diverse Redundant System for Safety Critical Applications in FPGA. ISVLSI 2010: 469-470
- [c50]Diana Göhringer, Michael Hübner, Laure Hugot-Derville, Jürgen Becker: Message Passing Interface support for the runtime adaptive multi-processor system-on-chip RAMPSoC. ICSAMOS 2010: 357-364
2000 – 2009
- 2009
- [j8]Diana Göhringer, Thomas Perschke, Michael Hübner, Jürgen Becker: A Taxonomy of Reconfigurable Single-/Multiprocessor Systems-on-Chip. Int. J. Reconfig. Comp. 2009 (2009)
- [j7]Michael Hübner, Juan Manuel Moreno, Gilles Sassatelli, Peter Zipf: Selected Papers from ReCoSoC 2008. Int. J. Reconfig. Comp. 2009 (2009)
- [j6]Lars Braun, Diana Göhringer, Thomas Perschke, Volker Schatz, Michael Hübner, Jürgen Becker: Adaptive real-time image processing exploiting two dimensional reconfigurable architecture. J. Real-Time Image Processing 4(2): 109-125 (2009)
- [j5]Katarina Paulsson, Michael Hübner, Jürgen Becker: Dynamic power optimization by exploiting self-reconfiguration in Xilinx Spartan 3-based systems. Microprocessors and Microsystems - Embedded Hardware Design 33(1): 46-52 (2009)
- [c49]Krzysztof Kepa, Fearghal Morgan, Krzysztof Kosciuszkiewicz, Lars Braun, Michael Hübner, Jürgen Becker: FPGA Analysis Tool: High-Level Flows for Low-Level Design Analysis in Reconfigurable Computing. ARC 2009: 62-73
- [c48]Diana Göhringer, Bin Liu, Michael Hübner, Jürgen Becker: Star-Wheels Network-on-Chip featuring a self-adaptive mixed topology and a synergy of a circuit - and a packet-switching communication protocol. FPL 2009: 320-325
- [c47]Romuald Girardey, Michael Hübner, Jürgen Becker: Dynamic reconfigurable mixed-signal architecture for safety critical applications. FPL 2009: 503-506
- [c46]Juan Fernando Eusse Giraldo, Michael Hübner, Ricardo Pezzuol Jacobi: BRICK: a multi-context expression grained reconfigurable architecture. SBCCI 2009
- [c45]Mahtab Niknahad, Michael Hübner, Jürgen Becker: Method for improving performance in online routing of reconfigurable nano architectures. SoCC 2009: 65-68
- 2008
- [j4]Matthias Kühnle, Michael Hübner, Jürgen Becker, Antonio Deledda, Claudio Mucci, Florian Ries, Marcello Coppola, Lorenzo Pieralisi, Riccardo Locatelli, Giuseppe Maruccia, Tommaso DeMarco, Fabio Campi: An Interconnect Strategy for a Heterogeneous, Reconfigurable SoC. IEEE Design & Test of Computers 25(5): 442-451 (2008)
- [j3]Jürgen Becker, Michael Hübner, Roger Woods, Philip Heng Wai Leong, Robert Esser, Lionel Torres: Current Trends on Reconfigurable Computing. Int. J. Reconfig. Comp. 2008 (2008)
- [c44]Oliver Sander, Lars Braun, Michael Hübner, Jürgen Becker: Data reallocation by exploiting FPGA configuration mechanisms. ARC 2008: 308-313
- [c43]Jürgen Becker, Michael Hübner, Robert Esser, Andreas Herkersdorf, Walter Stechele, Vera Lauer: Design Flows, Communication Based Design and Architectures in Automotive Electronic Systems. DATE 2008
- [c42]Katarina Paulsson, Michael Hübner, Jürgen Becker: Cost-and Power Optimized FPGA based System Integration: Methodologies and Integration of a Low-Power Capacity-based Measurement Application on Xilinx FPGAs. DATE 2008: 50-55
- [c41]Antonio Deledda, Claudio Mucci, Arseni Vitkovski, Philippe Bonnot, Arnaud Grasset, Philippe Millet, Matthias Kühnle, Florian Ries, Michael Hübner, Jürgen Becker, Massimo Coppola, Lorenzo Pieralisi, Riccardo Locatelli, Giuseppe Maruccia, Fabio Campi, Tommaso DeMarco: Design of a HW/SW Communication Infrastructure for a Heterogeneous Reconfigurable Processor. DATE 2008: 1352-1357
- [c40]Josef Angermeier, Mateusz Majer, Jürgen Teich, Lars Braun, Tobias Schwalb, Philipp Graf, Michael Hübner, Jürgen Becker, Enno Lübbers, Marco Platzner, Christopher Claus, Walter Stechele, Andreas Herkersdorf, Markus Rullmann, Renate Merker: Fine grain reconfigurable architectures. FPL 2008: 348
- [c39]Diana Göhringer, Michael Hübner, Thomas Perschke, Jürgen Becker: New dimensions for multiprocessor architectures: Ondemand heterogeneity, infrastructure and performance through reconfigurability - the RAMPSoC approach. FPL 2008: 495-498
- [c38]Christopher Claus, Bin Zhang, Walter Stechele, Lars Braun, Michael Hübner, Jürgen Becker: A multi-platform controller allowing for maximum Dynamic Partial Reconfiguration throughput. FPL 2008: 535-538
- [c37]Lars Braun, Katarina Paulsson, Herrmann Krömer, Michael Hübner, Jürgen Becker: Data path driven waveform-like reconfiguration. FPL 2008: 607-610
- [c36]Katarina Paulsson, Michael Hübner, Jürgen Becker: Exploitation of dynamic and partial hardware reconfiguration for on-line power/performance optimization. FPL 2008: 699-700
- [c35]Oliver Sander, Michael Hübner, Jürgen Becker, Matthias Traub: Reducing latency times by accelerated routing mechanisms for an FPGA gateway in the automotive domain. FPT 2008: 97-104
- [c34]Diana Göhringer, Michael Hübner, Volker Schatz, Jürgen Becker: Runtime adaptive multi-processor system-on-chip: RAMPSoC. IPDPS 2008: 1-7
- [c33]Michael Hübner, Lars Braun, Diana Göhringer, Jürgen Becker: Run-time reconfigurable adaptive multilayer network-on-chip for FPGA-based systems. IPDPS 2008: 1-6
- [c32]Christian Schuck, Matthias Kühnle, Michael Hübner, Jürgen Becker: A framework for dynamic 2D placement on FPGAs. IPDPS 2008: 1-7
- [c31]Katarina Paulsson, Ulrich Viereck, Michael Hübner, Jürgen Becker: Exploitation of the External JTAG Interface for Internally Controlled Configuration Readback and Self-Reconfiguration of Spartan 3 FPGAs. ISVLSI 2008: 304-309
- [c30]Juanjo Noguera, Robert Esser, Katarina Paulsson, Michael Hübner, Jürgen Becker: Towards Novel Approaches in Design Automation for FPGA Power Optimization. PATMOS 2008: 419-428
- 2007
- [c29]Katarina Paulsson, Michael Hübner, Günther Auer, Michael Dreschmann, Jürgen Becker: Implementation of a Virtual Internal Configuration Access Port (JCAP) for Enabling Partial Self-Reconfiguration on Xilinx Spartan III FPGAs. FPL 2007: 351-356
- [c28]Katarina Paulsson, Michael Hübner, Jürgen Becker, Jean-Marc Philippe, Christian Gamrat: On-line Routing of Reconfigurable Functions for Future Self-Adaptive Systems - Investigations within the ÆTHER Project. FPL 2007: 415-422
- [c27]Lars Braun, Michael Hübner, Jürgen Becker, Thomas Perschke, Volker Schatz, Stefan Bach: Circuit Switched Run-Time Adaptive Network-on-Chip for Image Processing Applications. FPL 2007: 688-691
- [c26]Philipp Graf, Michael Hübner, Klaus D. Müller-Glaser, Jürgen Becker: A Graphical Model-Level Debugger for Heterogenous Reconfigurable Architectures. FPL 2007: 722-725
- [c25]Thilo Pionteck, Carsten Albrecht, Roman Koch, Erik Maehle, Michael Hübner, Jürgen Becker: Communication Architectures for Dynamically Reconfigurable FPGA Designs. IPDPS 2007: 1-8
- [c24]Alisson Vasconcelos De Brito, Matthias Kühnle, Michael Hübner, Jürgen Becker, Elmar U. K. Melcher: Modelling and Simulation of Dynamic and Partially Reconfigurable Systems using SystemC. ISVLSI 2007: 35-40
- [c23]Michael Hübner, Lars Braun, Jürgen Becker, Christopher Claus, Walter Stechele: Physical Configuration On-Line Visualization of Xilinx Virtex-II FPGAs. ISVLSI 2007: 41-46
- [c22]Katarina Paulsson, Michael Hübner, Salih Bayar, Jürgen Becker: Exploitation of Run-Time Partial Reconfiguration for Dynamic Power Management in Xilinx Spartan III-based Systems. ReCoSoC 2007: 1-6
- [c21]Jürgen Becker, Adam Donlin, Michael Hübner: New tool support and architectures in adaptive reconfigurable computing. VLSI-SoC 2007: 134-139
- 2006
- [c20]Katarina Paulsson, Michael Hübner, Jürgen Becker: Strategies to On- Line Failure Recovery in Self- Adaptive Systems based on Dynamic and Partial Reconfiguration. AHS 2006: 288-291
- [c19]Jürgen Becker, Michael Hübner, Katarina Paulsson: Physical 2D Morphware and Power Reduction Methods for Everyone. Dynamically Reconfigurable Architectures 2006
- [c18]Michael Hübner, Christian Schuck, Jürgen Becker: Elementary block based 2-dimensional dynamic and partial reconfiguration for Virtex-II FPGAs. IPDPS 2006
- [c17]Michael Hübner, Christian Schuck, Matthias Kühnle, Jürgen Becker: New 2-Dimensional Partial Dynamic Reconfiguration Techniques for Real-time Adaptive Microelectronic Circuits. ISVLSI 2006: 97-102
- [c16]Katarina Paulsson, Michael Hübner, Markus Jung, Jürgen Becker: Methods for Run-time Failure Recognition and Recovery in dynamic and partial Reconfigurable Systems Based on Xilinx Virtex-II Pro FPGAs. ISVLSI 2006: 159-166
- [c15]Michael Hübner, Jürgen Becker: Exploiting dynamic and partial reconfiguration for FPGAs: toolflow, architecture and system integration. SBCCI 2006: 1-4
- [c14]Jürgen Becker, Michael Hübner: Run-time reconfigurabilility and other future trends. SBCCI 2006: 9-11
- [c13]Katarina Paulsson, Michael Hübner, Jürgen Becker: On-line optimization of FPGA power-dissipation by exploiting run-time adaption of communication primitives. SBCCI 2006: 173-178
- 2005
- [j2]Michael Ullmann, Michael Hübner, Jürgen Becker: On-demand FPGA run-time system for flexible and dynamical reconfiguration. IJES 1(3/4): 193-204 (2005)
- [j1]Michael Hübner, Michael Ullmann, Jürgen Becker: Realtime configuration code decompression for dynamic FPGA self reconfiguration: evaluation and implementation. IJES 1(3/4): 263-273 (2005)
- [c12]Michael Hübner, Katarina Paulsson, Marcus Stitz, Jürgen Becker: Novel Seamless Design-Flow for Partial and Dynamic Reconfigurable Systems with Customized Communication Structures based on Xilinx Virtex-II FPGAs. ARCS Workshops 2005: 39-44
- [c11]Matthias Riebisch, Michael Hübner: Traceability-Driven Model Refinement for Test Case Generation. ECBS 2005: 113-120
- [c10]Michael Hübner, Katarina Paulsson, Jürgen Becker: Parallel and Flexible Multiprocessor System-On-Chip for Adaptive Automotive Applications based on Xilinx MicroBlaze Soft-Cores. IPDPS 2005
- [c9]Jürgen Becker, Michael Hübner, Katarina Paulsson, Alexander Thomas: Dynamic Reconfiguration On-Demand: Real-time Adaptivity in Next Generation Microelectronics. ReCoSoC 2005: 35-42
- [c8]Adam Donlin, Jürgen Becker, Michael Hübner: I Models and Tools for the Dynamic Reconfiguration of FPGAs. SoCC 2005: 313-316
- 2004
- [c7]Michael Ullmann, Michael Hübner, Björn Grimm, Jürgen Becker: On-Demand FPGA Run-Time System for Dynamical Reconfiguration with Adaptive Priorities. FPL 2004: 454-463
- [c6]Brandon Blodget, Christophe Bobda, Michael Hübner, Adronis Niyonkuru: Partial and Dynamically Reconfiguration of Xilinx Virtex-II FPGAs. FPL 2004: 801-810
- [c5]Michael Hübner, Michael Ullmann, Lars Braun, A. Klausmann, Jürgen Becker: Scalable Application-Dependent Network on Chip Adaptivity for Dynamical Reconfigurable Real-Time Systems. FPL 2004: 1037-1041
- [c4]Michael Ullmann, Michael Hübner, Björn Grimm, Jürgen Becker: An FPGA Run-Time System for Dynamical On-Demand Reconfiguration. IPDPS 2004
- [c3]Michael Hübner, Tobias Becker, Jürgen Becker: Real-time LUT-based network topologies for dynamic and partial FPGA self-reconfiguration. SBCCI 2004: 28-32
- 2003
- [c2]Jürgen Becker, Michael Hübner, Michael Ullmann: Power Estimation and Power Measurement of Xilinx Virtex FPGAs: Trade-Offs and Limitations. SBCCI 2003: 283-288
- [c1]Jürgen Becker, Michael Hübner, Michael Ullmann: Real-Time Dynamically Run-Time Reconfiguration for Power-/Cost-optimized Virtex FPGA Realizations. VLSI-SOC 2003: 129-
Coauthor Index
[j17] [j16] [c92] [c91] [c90] [c89] [c88] [c86] [c85] [c83] [c82] [c81] [c80] [c79] [i1] [e2] [j13] [j12] [j11] [j10] [p2] [c78] [c77] [c76] [c75] [c74] [c73] [c72] [c71] [c70] [c69] [c68] [c67] [c66] [c65] [c64] [c63] [e1] [j9] [p1] [c62] [c60] [c59] [c58] [c56] [c55] [c54] [c53] [c52] [c51] [c50] [j8] [j6] [j5] [c49] [c48] [c47] [c45] [j4] [j3] [c44] [c43] [c42] [c41] [c40] [c39] [c38] [c37] [c36] [c35] [c34] [c33] [c32] [c31] [c30] [c29] [c28] [c27] [c26] [c25] [c24] [c23] [c22] [c21] [c20] [c19] [c18] [c17] [c16] [c15] [c14] [c13] [j2] [j1] [c12] [c10] [c9] [c8] [c7] [c5] [c4] [c3] [c2] [c1]
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last updated on 2013-04-24 23:04 CEST by the dblp team