Gary D. Hachtel

Gary D. Hachtel, Fabio Somenzi: Logic synthesis and verification algorithms. Springer 2006, isbn 978-0-387-31004-6, pp. I-XXIII, 1-564

Chao Wang, Roderick Bloem, Gary D. Hachtel, Kavita Ravi, Fabio Somenzi: Compositional SCC Analysis for Language Emptiness. Formal Methods in System Design 28(1): 5-36 (2006)

Chao Wang, Bing Li, HoonSang Jin, Gary D. Hachtel, Fabio Somenzi: Improving Ariadne's Bundle by Following Multiple Threads in Abstraction Refinement. IEEE Trans. on CAD of Integrated Circuits and Systems 25(11): 2297-2316 (2006)

Chao Wang, HoonSang Jin, Gary D. Hachtel, Fabio Somenzi: Refining the SAT decision ordering for bounded model checking. DAC 2004: 535-538

Chao Wang, Gary D. Hachtel, Fabio Somenzi: Fine-Grain Abstraction and Sequential Don't Cares for Large Scale Model Checking. ICCD 2004: 112-118

Chao Wang, Gary D. Hachtel, Fabio Somenzi: The Compositional Far Side of Image Computation. ICCAD 2003: 334-341

Chao Wang, Bing Li, HoonSang Jin, Gary D. Hachtel, Fabio Somenzi: Improving Ariadneýs Bundle by Following Multiple Threads in Abstraction Refinement. ICCAD 2003: 408-415

Chao Wang, Gary D. Hachtel: Sharp Disjunctive Decomposition for Language Emptiness Checking. FMCAD 2002: 106-122

Chao Wang, Roderick Bloem, Gary D. Hachtel, Kavita Ravi, Fabio Somenzi: Divide and Compose: SCC Refinement for Language Emptiness. CONCUR 2001: 456-471

Jae-Young Jang, In-Ho Moon, Gary D. Hachtel: Iterative Abstraction-Based CTL Model Checking. DATE 2000: 502-507

In-Ho Moon, Gary D. Hachtel, Fabio Somenzi: Border-Block Triangular Form and Conjunction Schedule in Image Computation. FMCAD 2000: 73-90

Abelardo Pardo, Gary D. Hachtel: Incremental CTL Model Checking Using BDD Subsetting. DAC 1998: 457-462

In-Ho Moon, Jae-Young Jang, Gary D. Hachtel, Fabio Somenzi, Jun Yuan, Carl Pixley: Approximate reachability don't cares for CTL model checking. ICCAD 1998: 351-358

R. Iris Bahar, Erica A. Frohm, Charles M. Gaona, Gary D. Hachtel, Enrico Macii, Abelardo Pardo, Fabio Somenzi: Algebraic Decision Diagrams and Their Applications. Formal Methods in System Design 10(2/3): 171-206 (1997)

Gary D. Hachtel, Fabio Somenzi: A Symbolic Algorithms for Maximum Flow in 0-1 Networks. Formal Methods in System Design 10(2/3): 207-219 (1997)

R. Iris Bahar, Hyunwoo Cho, Gary D. Hachtel, Enrico Macii, Fabio Somenzi: Symbolic timing analysis and resynthesis for low power of combinational circuits containing false paths. IEEE Trans. on CAD of Integrated Circuits and Systems 16(10): 1101-1115 (1997)

Abelardo Pardo, Gary D. Hachtel: Automatic Abstraction Techniques for Propositional µ-calculus Model Checking. CAV 1997: 12-23

Gary D. Hachtel, Fabio Somenzi: Logic synthesis and verification algorithms. Kluwer 1996, isbn 978-0-7923-9746-5, pp. I-XXIX, 1-564

Hyunwoo Cho, Gary D. Hachtel, Enrico Macii, Massimo Poncino, Fabio Somenzi: Automatic state space decomposition for approximate FSM traversal based on circuit analysis. IEEE Trans. on CAD of Integrated Circuits and Systems 15(12): 1451-1464 (1996)

Hyunwoo Cho, Gary D. Hachtel, Enrico Macii, Bernard Plessier, Fabio Somenzi: Algorithms for approximate FSM traversal based on state space decomposition. IEEE Trans. on CAD of Integrated Circuits and Systems 15(12): 1465-1478 (1996)

Gary D. Hachtel, Enrico Macii, Abelardo Pardo, Fabio Somenzi: Markovian analysis of large finite state machines. IEEE Trans. on CAD of Integrated Circuits and Systems 15(12): 1479-1493 (1996)

Robert K. Brayton, Gary D. Hachtel, Alberto L. Sangiovanni-Vincentelli, Fabio Somenzi, Adnan Aziz, Szu-Tsung Cheng, Stephen A. Edwards, Sunil P. Khatri, Yuji Kukimoto, Abelardo Pardo, Shaz Qadeer, Rajeev K. Ranjan, Shaker Sarwary, Thomas R. Shiple, Gitanjali Swamy, Tiziano Villa: VIS: A System for Verification and Synthesis. CAV 1996: 428-432

Kavita Ravi, Abelardo Pardo, Gary D. Hachtel, Fabio Somenzi: Modular Verification of Multipliers. FMCAD 1996: 49-63

Robert K. Brayton, Gary D. Hachtel, Alberto L. Sangiovanni-Vincentelli, Fabio Somenzi, Adnan Aziz, Szu-Tsung Cheng, Stephen A. Edwards, Sunil P. Khatri, Yuji Kukimoto, Abelardo Pardo, Shaz Qadeer, Rajeev K. Ranjan, Shaker Sarwary, Thomas R. Shiple, Gitanjali Swamy, Tiziano Villa: VIS. FMCAD 1996: 248-256

Woohyuk Lee, Abelardo Pardo, Jae-Young Jang, Gary D. Hachtel, Fabio Somenzi: Tearing based automatic abstraction for CTL model checking. ICCAD 1996: 76-81

R. Iris Bahar, M. Burns, Gary D. Hachtel, Enrico Macii, H. Shin, Fabio Somenzi: Symbolic computation of logic implications for technology-dependent low-power synthesis. ISLPED 1996: 163-168

Srilatha Manne, Abelardo Pardo, R. Iris Bahar, Gary D. Hachtel, Fabio Somenzi, Enrico Macii, Massimo Poncino: Computing the Maximum Power Cycles of a Sequential Circuit. DAC 1995: 23-28

Abelardo Pardo, R. Iris Bahar, Srilatha Manne, Peter Feldmann, Gary D. Hachtel, Fabio Somenzi: CMOS dynamic power estimation based on collapsible current source transistor modeling. ISLPD 1995: 111-116

Bernard Plessier, Gary D. Hachtel, Fabio Somenzi: Extended BDDs: Trading off Canonicity for Structure in Verification Algorithms. Formal Methods in System Design 4(2): 167-185 (1994)

June-Kyung Rho, Gary D. Hachtel, Fabio Somenzi, Reily M. Jacoby: Exact and heuristic algorithms for the minimization of incompletely specified state machines. IEEE Trans. on CAD of Integrated Circuits and Systems 13(2): 167-177 (1994)

Carl Pixley, Seh-Woong Jeong, Gary D. Hachtel: Exact calculation of synchronizing sequences based on binary decision diagrams. IEEE Trans. on CAD of Integrated Circuits and Systems 13(8): 1024-1034 (1994)

Gary D. Hachtel, Enrico Macii, Abelardo Pardo, Fabio Somenzi: Probabilistic Analysis of Large Finite State Machines. DAC 1994: 270-275

Hyunwoo Cho, Gary D. Hachtel, Enrico Macii, Massimo Poncino, Fabio Somenzi: A State Space Decomposition Algorithm for Approximate FSM Traversal. EDAC-ETC-EUROASIC 1994: 137-141

Gary D. Hachtel, Enrico Macii, Abelardo Pardo, Fabio Somenzi: Symbolic Algorithms to Calculate Steady-State Probabilities of a Finite State Machine. EDAC-ETC-EUROASIC 1994: 214-218

R. Iris Bahar, Hyunwoo Cho, Gary D. Hachtel, Enrico Macii, Fabio Somenzi: Timing Analysis of Combinational Circuits using ADD's. EDAC-ETC-EUROASIC 1994: 625-629

Gary D. Hachtel, Mariano Hermida de la Rica, Abelardo Pardo, Massimo Poncino, Fabio Somenzi: Re-encoding sequential circuits to reduce power dissipation. ICCAD 1994: 70-73

R. Iris Bahar, Gary D. Hachtel, Enrico Macii, Fabio Somenzi: A symbolic method to reduce power consumption of circuits containing false paths. ICCAD 1994: 368-371

Hyunwoo Cho, Gary D. Hachtel, Enrico Macii, Massimo Poncino, Fabio Somenzi: A Structural Approach to State Space Decomposition for Approximate Reachability Analysis. ICCD 1994: 236-239

Hyunwoo Cho, Gary D. Hachtel, Fabio Somenzi: Redundancy identification/removal and test generation for sequential circuits using implicit state enumeration. IEEE Trans. on CAD of Integrated Circuits and Systems 12(7): 935-945 (1993)

Hyunwoo Cho, Gary D. Hachtel, Enrico Macii, Bernard Plessier, Fabio Somenzi: Algorithms for Approximate FSM Traversal. DAC 1993: 25-30

R. Iris Bahar, Erica A. Frohm, Charles M. Gaona, Gary D. Hachtel, Enrico Macii, Abelardo Pardo, Fabio Somenzi: Algebraic decision diagrams and their applications. ICCAD 1993: 188-191

Gary D. Hachtel, Fabio Somenzi: A symbolic algorithm for maximum flow in 0-1 networks. ICCAD 1993: 403-406

Gary D. Hachtel, Reily M. Jacoby, Kurt Keutzer, Christopher R. Morrison: On properties of algebraic transformations and the synthesis of multifault-irredundant circuits. IEEE Trans. on CAD of Integrated Circuits and Systems 11(3): 313-321 (1992)

Carl Pixley, Seh-Woong Jeong, Gary D. Hachtel: Exact Calculation of Synchronization Sequences Based on Binary Decision Diagrams. DAC 1992: 620-623

Xuejun Du, Gary D. Hachtel, Bill Lin, A. Richard Newton: MUSE: a multilevel symbolic encoding algorithm for state assignment. IEEE Trans. on CAD of Integrated Circuits and Systems 10(1): 28-38 (1991)

June-Kyung Rho, Gary D. Hachtel, Fabio Somenzi: Don't Care Sequences and the Optimization of Interacting Finite State Machines. ICCAD 1991: 418-421

Seh-Woong Jeong, Bernard Plessier, Gary D. Hachtel, Fabio Somenzi: Extended BDD's: Trading off Canonicity for Structure in Verification Algorithms. ICCAD 1991: 464-467

Seon-Woong Jeong, Bernard Plessier, Gary D. Hachtel, Fabio Somenzi: Variable Ordering and Selection for FSM Traversal. ICCAD 1991: 476-479

Hyunwoo Cho, Gary D. Hachtel, Fabio Somenzi: Redundancy Identification and Removal Based on Implicit State Enumeration. ICCD 1991: 77-80

Hyunwoo Cho, Gary D. Hachtel, Fabio Somenzi: Fast Sequential ATPG Based on Implicit State Enumeration. ITC 1991: 67-74

Hyunwoo Cho, Gary D. Hachtel, Seh-Woong Jeong, Bernard Plessier, Eric M. Schwarz, Fabio Somenzi: ATPG Aspects of FSM Verification. ICCAD 1990: 134-137

Gary D. Hachtel, Christopher R. Morrison: Linear complexity algorithms for hierarchical routing. IEEE Trans. on CAD of Integrated Circuits and Systems 8(1): 64-80 (1989)

Gary D. Hachtel, Reily M. Jacoby: Verification algorithms for VLSI synthesis. IEEE Trans. on CAD of Integrated Circuits and Systems 7(5): 616-640 (1988)

Karen A. Bartlett, Robert K. Brayton, Gary D. Hachtel, Reily M. Jacoby, Christopher R. Morrison, Richard L. Rudell, Alberto L. Sangiovanni-Vincentelli, Albert R. Wang: Multi-level logic minimization using implicit don't cares. IEEE Trans. on CAD of Integrated Circuits and Systems 7(6): 723-740 (1988)

Karen A. Bartlett, William W. Cohen, Aart J. de Geus, Gary D. Hachtel: Synthesis and Optimization of Multilevel Logic under Timing Constraints. IEEE Trans. on CAD of Integrated Circuits and Systems 5(4): 582-596 (1986)

David Gregory, Karen A. Bartlett, Aart J. de Geus, Gary D. Hachtel: SOCRATES: a system for automatically synthesizing and optimizing combinational logic. DAC 1986: 79-85

Michael R. Lightner, Gary D. Hachtel, Richard H. Byrd, Michel Heydemann: A Theory and Algorithmic Frame for Switch Level Simulation. IMACS European Simulation Meeting 1984: 151-159

Gary D. Hachtel, A. Richard Newton, Alberto L. Sangiovanni-Vincentelli: An Algorithm for Optimal PLA Folding. IEEE Trans. on CAD of Integrated Circuits and Systems 1(2): 63-77 (1982)

Gary D. Hachtel, A. Richard Newton, Alberto L. Sangiovanni-Vincentelli: Techniques for programmable logic array folding. DAC 1982: 147-155

Michael R. Lightner, Gary D. Hachtel: Implication algorithms for MOS switch level functional macromodeling implication and testing. DAC 1982: 691-698