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Vladimir Hahanov
2010 – today
- 2013
[j5]SooKyun Kim, Henry Duh, Nabil J. Sarhan, Vladimir Hahanov: Real-time multimedia computing. Multimedia Tools Appl. 65(2): 181-186 (2013)- 2012
- [i4]Vladimir Hahanov, Wajeb Gharibi, Eugenia Litvinova, Svetlana Chumachenko: Information Analysis Infrastructure for Diagnosis. CoRR abs/1201.0954 (2012)
- [i3]Vladimir Hahanov, Wajeb Gharibi, Eugenia Litvinova, Svetlana Chumachenko: Verification and Diagnosis Infrastructure of SoC HDL-model. CoRR abs/1203.0665 (2012)
- 2011
- [c25]Vladimir Hahanov, Wajeb Gharibi, Dong-Won Park, Eugenia Litvinova: Cybercomputer for information space analysis. EWDTS 2011: 66-71
- [c24]Vladimir Hahanov, Dong-Won Park, Olesya Guz, Aleksey Priymak: Verification and diagnosis of SoC HDL-code. EWDTS 2011: 72-83
- [c23]Tiecoura Yves, Vladimir Hahanov, Omar Alnahhal, Mikhail Maksimov, Dmitry Shcherbin, Dmitry Yudin: Diagnosis infrastructure of software-hardware systems. EWDTS 2011: 84-89
- [c22]Vladimir Hahanov, Aleksandr Mischenko, Svetlana Chumachenko, Anna Hahanova, Alexey Priymak: Spam diagnosis infrastructure for individual cyberspace. EWDTS 2011: 161-168
- [c21]
- [c20]Vladimir Hahanov, Karyna Mostova, Oleksandr Paschenko: Infrastructure for testing and diagnosing multimedia devices. EWDTS 2011: 394-399
- [e1]Vladimir Hahanov, Yervant Zorian (Eds.): 9th East-West Design & Test Symposium, EWDTS 2011, Sevastopol, Ukraine, September 9-12, 2011. IEEE 2011, ISBN 978-1-4577-1957-8
- [i2]Vladimir Hahanov, Eugenia Litvinova, Wajeb Gharibi, Olesya Guz: Algebra-Logical Repair Method for FPGA Logic Blocks. CoRR abs/1105.1967 (2011)
- [i1]Vladimir Hahanov, Wajeb Gharibi, Olesya Guz: Brain-like infrastructure for embedded SoC diagnosis. CoRR abs/1105.1973 (2011)
- 2010
- [c19]Vladimir Hahanov, Eugenia Litvinova, Wajeb Gharibi, Olesya Guz: Coverage method for FPGA fault logic blocks by spares. EWDTS 2010: 51-56
- [c18]Vladimir Hahanov, Irina Hahanova, Ngene Christopher Umerah, Tiecoura Yves: Testing and verification of HDL-models for SoC components. EWDTS 2010: 77-82
- [c17]Vladimir Hahanov, Wajeb Gharibi, Eugenia Litvinova, Svetlana Chumachenko: Cyber space and brain-like computing. EWDTS 2010: 98-109
- [c16]Vladimir Hahanov, Wajeb Gharibi, Svetlana Chumachenko, Eugenia Litvinova: Vector logic analysis of associative matrices. EWDTS 2010: 110-117
- [c15]Vladimir Hahanov, Eugenia Litvinova, Aleksey Priymak: Table data structures for cyber space. EWDTS 2010: 118-122
- [c14]Vladimir Hahanov, Olesya Guz, Ngene Christopher Umerah, Vitaliy Olchovoy: Process models for analyzing associative data structures. EWDTS 2010: 123-127
- [c13]Vladimir Hahanov, Alexander Mishchenko, Vitaliy Varetsa: Metrics of vector logic algebra for cyber space. EWDTS 2010: 204-207
- [c12]
- [c11]Vladimir Hahanov, Irina Pobizhenko, Tiecoura Yves: Logical method for detecting faults by fault detection table. EWDTS 2010: 215-217
- [c10]Alexander Adamov, Vladimir Hahanov: Security risks in hardware: Implementation and detection problem. EWDTS 2010: 425-427
- [c9]Vladimir Hahanov, Aleksey Sushanov, Yulia Stepanova, Alexander Gorobets: System in Package. Diagnosis and embedded repair. EWDTS 2010: 468-472
- [c8]Vladimir Hahanov, Svetlana Chumachenko, Eugenia Litvinova, Oleg Zakharchenko, Natalya Kulbakova: Technology for faulty blocks coverage by spares. EWDTS 2010: 473-478
- [c7]Vladimir Hahanov, Sergey Galagan, Vitaliy Olchovoy, Aleksey Priymak: Algebra-logical repair method for FPGA logic blocks. EWDTS 2010: 482-487
2000 – 2009
- 2008
- [c6]Vladimir Hahanov, Eugenia Litvinova, Karina Krasnoyaruzhskaya, Sergey Galagan: Diagnosis of SoC faulty memory cells for embedded repair. EWDTS 2008: 143-148
- [c5]Vladimir Hahanov, Olesya Guz, Natalya Kulbakova, Maxim Davydov: Vector-logical diagnosis method for SOC functionalities. EWDTS 2008: 159-162
- 2006
- [j4]Vladimir Hahanov: East-West Design & Test Workshop. IEEE Design & Test of Computers 23(6): 504-505 (2006)
- 2005
- [j3]Vladimir Hahanov: 2005 IEEE East-West Design and Test Workshop. IEEE Design & Test of Computers 22(6): 600 (2005)
- [c4]Stanley Hyduke, Vladimir Hahanov, Volodymyr Obrizan, Olesya Guz: PRUS - Processor Network for Digital Circuit Implementation. DSD 2005: 239-242
- 2004
- [j2]Vladimir Hahanov, Raimund Ubar, Subhasish Mitra: Conference Reports. IEEE Design & Test of Computers 21(6): 594-595 (2004)
- [c3]Vladimir Hahanov, Irina Hahanova, Stanley Hyduke: Topological BDP Fault Simulation Method. DSD 2004: 440-443
- 2003
- [j1]Vladimir Hahanov, Raimund Ubar: Conference Reports. IEEE Design & Test of Computers 20(6): 103- (2003)
- [c2]Vladimir Hahanov, Raimund Ubar, Stanley Hyduke: Back-Traced Deductive-Parallel Fault Simulation for Digital Systems. DSD 2003: 370-377
- 2001
- [c1]Vladimir Hahanov, Anna Babich: Test Generation and Fault Simulation Methods on the Basis of Cubic Algebra for Digital Devices. DSD 2001: 228-235
Coauthor Index
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last updated on 2013-05-15 22:00 CEST by the dblp team