| 2011 | ||
|---|---|---|
| j3 | Mazad S. Zaveri, Dan W. Hammerstrom: Performance/price estimates for cortex-scale hardware: A design space exploration. Neural Networks 24(3): 291-304 (2011) | |
| 2008 | ||
| c6 | Changjian Gao, Mazad S. Zaveri, Dan W. Hammerstrom: CMOS / CMOL architectures for spiking cortical column. IJCNN 2008: 2441-2448 | |
| 2007 | ||
| j2 | R. Iris Bahar, Dan W. Hammerstrom, Justin E. Harlow III, William H. Joyner Jr., Clifford Lau, Diana Marculescu, Alex Orailoglu, Massoud Pedram: Architectures for Silicon Nanoelectronics and Beyond. IEEE Computer 40(1): 25-33 (2007) | |
| i1 | William N. N. Hung, Changjian Gao, Xiaoyu Song, Dan W. Hammerstrom: Defect-Tolerant CMOL Cell Assignment via Satisfiability. CoRR abs/0705.4320 (2007) | |
| 2000 | ||
| c5 | ||
| 1995 | ||
| c4 | ||
| 1993 | ||
| j1 | Dan W. Hammerstrom, Steven Rehfuss: Neurocomputing hardware: present and future. Artif. Intell. Rev. 7(5): 285-300 (1993) | |
| 1987 | ||
| c3 | ||
| 1982 | ||
| c2 | Fred J. Pollack, George W. Cox, Dan W. Hammerstrom, Kevin C. Kahn, Konrad K. Lai, Justin R. Rattner: Supporting Ada Memory Management in the iAPX-432. ASPLOS 1982: 117-131 | |
| 1977 | ||
| c1 | Dan W. Hammerstrom, Edward S. Davidson: Information Content of CPU Memory Referencing Behavior. ISCA 1977: 184-192 | |
Colors in the list of coauthors
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