| 2011 | ||
|---|---|---|
| j8 | Andreas Hansson, Kees Goossens: A quantitative evaluation of a Network on Chip design flow for multi-core consumer multimedia applications. Design Autom. for Emb. Sys. 15(2): 159-190 (2011) | |
| j7 | Andreas Hansson, Marcus Ekerhult, Anca Mariana Molnos, Aleksandar Milutinovic, Andrew Nelson, Jude Angelo Ambrose, Kees Goossens: Design and implementation of an operating system for composable processor sharing. Microprocessors and Microsystems - Embedded Hardware Design 35(2): 246-260 (2011) | |
| p1 | Benny Akesson, Anca Mariana Molnos, Andreas Hansson, Jude Angelo Ambrose, Kees Goossens: Composability and Predictability for Independent Application Development, Verification, and Execution. Multiprocessor System-on-Chip 2011: 25-56 | |
| 2010 | ||
| c13 | Kees Goossens, Andreas Hansson: The aethereal network on chip after ten years: goals, evolution, lessons, and future. DAC 2010: 306-311 | |
| c12 | Andrew Nelson, Andreas Hansson, Henk Corporaal, Kees G. W. Goossens: Conservative application-level performance analysis through simulation of MPSoCs. ESTImedia 2010: 51-60 | |
| 2009 | ||
| j6 | Andreas Hansson, Maarten Wiggers, Arno Moonen, Kees Goossens, Marco Bekooij: Enabling application-level performance guarantees in network-based systems on chip by applying dataflow analysis. IET Computers & Digital Techniques 3(5): 398-412 (2009) | |
| j5 | Andreas Hansson, Benny Akesson, Jef L. van Meerbergen: Multi-processor programming in the embedded system curriculum. SIGBED Review 6(1): 9 (2009) | |
| j4 | Andreas Hansson, Kees Goossens, Marco Bekooij, Jos Huisken: CoMPSoC: A template for composable and predictable multi-processor system on chips. ACM Trans. Design Autom. Electr. Syst. 14(1) (2009) | |
| c11 | Andreas Hansson, Kees Goossens: An on-chip interconnect and protocol stack for multiple communication paradigms and programming models. CODES+ISSS 2009: 99-108 | |
| c10 | Andreas Hansson, Mahesh Subburaman, Kees Goossens: Aelite: A flit-synchronous Network on Chip with composable and predictable services. DATE 2009: 250-255 | |
| c9 | Benny Akesson, Andreas Hansson, Kees Goossens: Composable Resource Sharing Based on Latency-Rate Servers. DSD 2009: 547-555 | |
| 2008 | ||
| j3 | Calin Ciordas, Andreas Hansson, Kees Goossens, Twan Basten: A monitoring-aware network-on-chip design flow. Journal of Systems Architecture - Embedded Systems Design 54(3-4): 397-410 (2008) | |
| c8 | Andreas Hansson, Maarten Wiggers, Arno Moonen, Kees Goossens, Marco Bekooij: Applying Dataflow Analysis to Dimension Buffers for Guaranteed Performance in Networks on Chip. NOCS 2008: 211-212 | |
| 2007 | ||
| j2 | Andreas Hansson, Kees Goossens, Andrei Radulescu: Avoiding Message-Dependent Deadlock in Network-Based Systems on Chip. VLSI Design 2007 (2007) | |
| j1 | Andreas Hansson, Kees Goossens, Andrei Radulescu: A Unified Approach to Mapping and Routing on a Network-on-Chip for Both Best-Effort and Guaranteed Service Traffic. VLSI Design 2007 (2007) | |
| c7 | Andreas Hansson, Martijn Coenen, Kees Goossens: Channel trees: reducing latency by sharing time slots in time-multiplexed networks on chip. CODES+ISSS 2007: 149-154 | |
| c6 | Akash Kumar, Andreas Hansson, Jos Huisken, Henk Corporaal: Interactive presentation: An FPGA design flow for reconfigurable network-based multi-processor systems on chip. DATE 2007: 117-122 | |
| c5 | Andreas Hansson, Martijn Coenen, Kees Goossens: Undisrupted quality-of-service during reconfiguration of multiple applications in networks on chip. DATE 2007: 954-959 | |
| c4 | Andreas Hansson, Kees Goossens: Trade-offs in the Configuration of a Network on Chip for Multiple Use-Cases. NOCS 2007: 233-242 | |
| 2006 | ||
| c3 | Calin Ciordas, Andreas Hansson, Kees Goossens, Twan Basten: A Monitoring-Aware Network-on-Chip Design Flow. DSD 2006: 97-106 | |
| c2 | Andreas Hansson, Lars Niklasson: Using Segmentation to Control the Retrieval of Data. IJCNN 2006: 1764-1769 | |
| 2005 | ||
| c1 | Andreas Hansson, Kees Goossens, Andrei Radulescu: A unified approach to constrained mapping and routing on network-on-chip architectures. CODES+ISSS 2005: 75-80 | |
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