Takahiro Hanyu

Masanori Natsui, Daisuke Suzuki, Noboru Sakimura, Ryusuke Nebashi, Yukihide Tsuji, Ayuka Morioka, Tadahiko Sugibayashi, Sadahiko Miura, Hiroaki Honjo, Keizo Kinoshita, Shoji Ikeda, Tetsuo Endoh, Hideo Ohno, Takahiro Hanyu: Nonvolatile logic-in-memory array processor in 90nm MTJ/MOS achieving 75% leakage reduction using cycle-based power gating. ISSCC 2013: 194-195

Naoya Onizawa, Atsushi Matsumoto, Takahiro Hanyu: Long-Range Asynchronous On-Chip Link Based on Multiple-Valued Single-Track Signaling. IEICE Transactions 95-A(6): 1018-1029 (2012)

Masanori Natsui, Takashi Arimitsu, Takahiro Hanyu: Low-Energy Pipelined Multiple-Valued Current-Mode Circuit Based on Current-Level Control Technique. Multiple-Valued Logic and Soft Computing 19(1-3): 219-231 (2012)

Shoun Matsunaga, Masanori Natsui, Shoji Ikeda, Katsuya Miura, Tetsuo Endoh, Hideo Ohno, Takahiro Hanyu: Implementation of a perpendicular MTJ-based read-disturb-tolerant 2T-2R nonvolatile TCAM based on a reversed current reading scheme. ASP-DAC 2012: 475-476

Naoya Onizawa, Shoun Matsunaga, Vincent C. Gaudet, Takahiro Hanyu: High-Throughput Low-Energy Content-Addressable Memory Based on Self-Timed Overlapped Search Mechanism. ASYNC 2012: 41-48

Noboru Sakimura, Ryusuke Nebashi, Yukihide Tsuji, Hiroaki Honjo, Tadahiko Sugibayashi, Hiroki Koike, Takashi Ohsawa, Shunsuke Fukami, Takahiro Hanyu, Hideo Ohno, Tetsuo Endoh: High-speed simulator including accurate MTJ models for spintronics integrated circuit design. ISCAS 2012: 1971-1974

Youngkeun Kim, Masanori Natsui, Takahiro Hanyu: Variation-resilient current-mode logic circuit design using MTJ devices. ISCAS 2012: 2705-2708

Atsushi Matsumoto, Naoya Onizawa, Takahiro Hanyu: Systematic Coding Schemes for Low-Power Multiple-Valued Current-Mode Asynchronous Communication Links. ISMVL 2012: 13-18

Naoya Onizawa, Vincent C. Gaudet, Takahiro Hanyu, Warren J. Gross: Asynchronous Stochastic Decoding of Low-Density Parity-Check Codes. ISMVL 2012: 92-97

Shoun Matsunaga, Takahiro Hanyu: Quaternary 1T-2MTJ Cell Circuit for a High-Density and a High-Throughput Nonvolatile Bit-Serial CAM. ISMVL 2012: 98-103

Masanori Natsui, Takaaki Nagashima, Takahiro Hanyu: Process-Variation-Resilient OTA Using MTJ-based Multi-level Resistance Control. ISMVL 2012: 214-219

Luca Montesi, Zeljko Zilic, Takahiro Hanyu, Daisuke Suzuki: Building Blocks to Use in Innovative Non-volatile FPGA Architecture Based on MTJs. ISVLSI 2012: 302-307

Tomohiro Yoneda, Masashi Imai, Naoya Onizawa, Atsushi Matsumoto, Takahiro Hanyu: Multi-chip NoCs for Automotive Applications. PRDC 2012: 105-110

Naoya Onizawa, Warren J. Gross, Takahiro Hanyu, Vincent C. Gaudet: Clockless Stochastic Decoding of Low-Density Parity-Check Codes. SiPS 2012: 143-148

Satoru Hanzawa, Takahiro Hanyu: Design of an 8-nsec 72-bit-Parallel-Search Content-Addressable Memory Using a Phase-Change Device. IEICE Transactions 94-C(8): 1302-1310 (2011)

Naoya Onizawa, Vincent C. Gaudet, Takahiro Hanyu: Low-Energy Asynchronous Interleaver for Clockless Fully Parallel LDPC Decoding. IEEE Trans. on Circuits and Systems 58-I(8): 1933-1943 (2011)

Naoya Onizawa, Atsushi Matsumoto, Takahiro Hanyu: Interconnect-fault-resilient delay-insensitive asynchronous communication link based on current-flow monitoring. DATE 2011: 776-781

Takahiro Hanyu: Instant power-on nonvolatile FPGA based on MTJ/MOS-hybrid circuitry. ACM Great Lakes Symposium on VLSI 2011: 437-438

Takao Kawano, Naoya Onizawa, Atsushi Matsumoto, Takahiro Hanyu: Adjacent-State monitoring based fine-grained power-gating scheme for a low-power asynchronous pipelined system. ISCAS 2011: 2067-2070

Shoun Matsunaga, Akira Katsumata, Masanori Natsui, Takahiro Hanyu: Design of a Low-Energy Nonvolatile Fully-Parallel Ternary CAM Using a Two-Level Segmented Match-Line Scheme. ISMVL 2011: 99-104

Atsushi Matsumoto, Naoya Onizawa, Takahiro Hanyu: Complementary Multiple-Valued Encoding Scheme for Interconnect-Fault-Resilient Bidirectional Asynchronous Links. ISMVL 2011: 236-241

Masashi Kamiyanagi, Fumitaka Iga, Shoji Ikeda, Katsuya Miura, Jun Hayakawa, Haruhiro Hasegawa, Takahiro Hanyu, Hideo Ohno, Tetsuo Endoh: Transient Characteristic of Fabricated Magnetic Tunnel Junction (MTJ) Programmed with CMOS Circuit. IEICE Transactions 93-C(5): 602-607 (2010)

Fumitaka Iga, Masashi Kamiyanagi, Shoji Ikeda, Katsuya Miura, Jun Hayakawa, Haruhiro Hasegawa, Takahiro Hanyu, Hideo Ohno, Tetsuo Endoh: Study of the DC Performance of Fabricated Magnetic Tunnel Junction Integrated on Back-End Metal Line of CMOS Circuits. IEICE Transactions 93-C(5): 608-613 (2010)

Hirokatsu Shirahama, Takashi Matsuura, Masanori Natsui, Takahiro Hanyu: Energy-Aware Multiple-Valued Current-Mode Sequential Circuits Using a Completion-Detection Scheme. IEICE Transactions 93-D(8): 2080-2088 (2010)

Naoya Onizawa, Takahiro Hanyu: Highly Reliable Multiple-Valued One-Phase Signalling for an Asynchronous On-Chip Communication Link. IEICE Transactions 93-D(8): 2089-2099 (2010)

Naoya Onizawa, Takahiro Hanyu, Vincent C. Gaudet: Design of High-Throughput Fully Parallel LDPC Decoders Based on Wire Partitioning. IEEE Trans. VLSI Syst. 18(3): 482-489 (2010)

Naoya Onizawa, Takahiro Hanyu: High-throughput protocol converter based on an independent encoding/decoding scheme for asynchronous Network-on-Chip. ISCAS 2010: 157-160

Atsushi Matsumoto, Naoya Onizawa, Takahiro Hanyu: One-Color Two-Phase Asynchronous Communication Links Based on Multiple-Valued Simultaneous Control. ISMVL 2010: 211-216

Masanori Natsui, Takashi Arimitsu, Takahiro Hanyu: Low-Energy Pipelined Multiple-Valued Current-Mode Circuit with 8-Level Static Current-Source Control. ISMVL 2010: 235-240

Naoya Onizawa, Tomoyoshi Funazaki, Atsushi Matsumoto, Takahiro Hanyu: Accurate Asynchronous Network-on-Chip Simulation Based on a Delay-Aware Model. ISVLSI 2010: 357-362

Takahiro Hanyu: Special session 8B: New topic MOS/MTJ-hybrid circuit with nonvolatile logic-in-memory architecture and its impact. VTS 2010: 258

Naoya Onizawa, Takahiro Hanyu, Vincent C. Gaudet: High-Throughput Bit-Serial LDPC Decoder LSI Based on Multiple-Valued Asynchronous Interleaving. IEICE Transactions 92-C(6): 867-874 (2009)

Shoun Matsunaga, Jun Hayakawa, Shoji Ikeda, Katsuya Miura, Tetsuo Endoh, Hideo Ohno, Takahiro Hanyu: MTJ-based nonvolatile logic-in-memory circuit, future prospects and issues. DATE 2009: 433-435

Yo Ohtake, Naoya Onizawa, Takahiro Hanyu: High-performance Asynchronous Intra-chip Communication Link based on a Multiple-valued Current-mode Single-track Scheme. ISCAS 2009: 1000-1003

Naoya Onizawa, Takahiro Hanyu: Robust Multiple-Valued Current-Mode Circuit Components Based on Adaptive Reference-Voltage Control. ISMVL 2009: 36-41

Takashi Matsuura, Hirokatsu Shirahama, Masanori Natsui, Takahiro Hanyu: Timing-Variation-Aware Multiple-Valued Current-Mode Circuit for a Low-Power Pipelined System. ISMVL 2009: 60-65

Kazuyasu Mizusawa, Naoya Onizawa, Takahiro Hanyu: Power-Aware Asynchronous Peer-to-Peer Duplex Communication System Based on Multiple-Valued One-Phase Signaling. IEICE Transactions 91-C(4): 581-588 (2008)

Masatomo Miura, Takahiro Hanyu: Highly Reliable Multiple-Valued Current-Mode Comparator Based on Active-Load Dual-Rail Operation. IEICE Transactions 91-C(4): 589-594 (2008)

Hirokatsu Shirahama, Takahiro Hanyu: Design of High-Performance Quaternary Adders Based on Output-Generator Sharing. ISMVL 2008: 8-13

Akihiro Hirosaki, Masatomo Miura, Atsushi Matsumoto, Takahiro Hanyu: Vth-Variation Compensation of Multiple-Valued Current-Mode Circuit Using TMR Devices. ISMVL 2008: 14-19

Tasuku Nagai, Naoya Onizawa, Takahiro Hanyu: High-Speed Timing Verification Scheme Using Delay Tables for a Large-Scaled Multiple-Valued Current-Mode Circuit. ISMVL 2008: 70-75

Akira Mochizuki, Hirokatsu Shirahama, Takahiro Hanyu: Design and Evaluation of a 54 x 54-bit Multiplier Based on Differential-Pair Circuitry. IEICE Transactions 90-C(4): 683-691 (2007)

Shoun Matsunaga, Takahiro Hanyu, Hiromitsu Kimura, T. Nakamura, H. Takasu: Implementation of a Standby-Power-Free CAM Based on Complementary Ferroelectric-Capacitor Logic. ASP-DAC 2007: 116-117

Hirokatsu Shirahama, Akira Mochizuki, Takahiro Hanyu, Masami Nakajima, Kazutami Arimoto: Design of a Processing Element Based on Quaternary Differential Logic for a Multi-Core SIMD Processor. ISMVL 2007: 43

Tomohiro Takahashi, Kazuyasu Mizusawa, Takahiro Hanyu: Asynchronous Peer-to-Peer Simplex/Duplex-Compatible Communication System Using a One-Phase Signaling Scheme. ISMVL 2007: 44

Akira Mochizuki, Masatomo Miura, Takahiro Hanyu: High-Performance Multiple-Valued Comparator Based on Active-Load Dual-Rail Differential Logic for Crosstalk-Noise Reduction. ISMVL 2007: 57

Takahiro Hanyu: Special Section on Novel Device Architectures and System Integration Technologies. IEICE Transactions 89-C(11): 1491 (2006)

Naoya Onizawa, Takahiro Hanyu: Design and Evaluation of a NULL-Convention Circuit Based on Dual-Rail Current-Mode Differential Logic. IEICE Transactions 89-C(11): 1575-1580 (2006)

Akira Mochizuki, Hirokatsu Shirahama, Takahiro Hanyu: Design of a Low-Power Quaternary Flip-Flop Based on Dynamic Differential Logic. IEICE Transactions 89-C(11): 1591-1597 (2006)

Tomohiro Takahashi, Takahiro Hanyu: Implementation of a High-Speed Asynchronous Data-Transfer Chip Based on Multiple-Valued Current-Signal Multiplexing. IEICE Transactions 89-C(11): 1598-1604 (2006)

Akira Mochizuki, Takahiro Hanyu: Highly reliable Multiple-Valued Circuit Based on Dual-Rail Differential Logic. ISMVL 2006: 5

Akira Mochizuki, Takeshi Kitamura, Hirokatsu Shirahama, Takahiro Hanyu: Design of a Microprocessor Datapath Using Four-Valued Differential-Pair Circuits. ISMVL 2006: 14

Akira Mochizuki, Hiromitsu Kimura, Mitsuru Ibuki, Takahiro Hanyu: TMR-Based Logic-in-Memory Circuit for Low-Power VLSI. IEICE Transactions 88-A(6): 1408-1415 (2005)

Naoya Onizawa, Akira Mochizuki, Takahiro Hanyu: Multiple-Valued Duplex Asynchronous Data Transfer Scheme for Interleaving in LDPC Decoders. ISMVL 2005: 138-143

Tomohiro Takahashi, Takahiro Hanyu: Multiple-Valued Multiple-Rail Encoding Scheme for Low-Power Asynchronous Communication. ISMVL 2004: 20-25

Akira Mochizuki, Takashi Takeuchi, Takahiro Hanyu: Intra-Chip Address-Presetting Data-Transfer Scheme Using Four-Valued Encoding. ISMVL 2004: 192-197

Hiromitsu Kimura, Kostas Pagiamtzis, Ali Sheikholeslami, Takahiro Hanyu: A Study of Multiple-Valued Magnetoresistive RAM (MRAM) Using Binary MTJ Devices. ISMVL 2004: 340-345

Takahiro Hanyu, Tomohiro Takahashi, Michitaka Kameyama: Bidirectional Data Transfer Based Asynchronous VLSI System Using Multiple-Valued Current Mode Logic. ISMVL 2003: 99-104

Takahiro Hanyu, Akira Mochizuki, Michitaka Kameyama: Multiple-Valued Dynamic Source-Coupled Logic. ISMVL 2003: 207-212

Hiromitsu Kimura, Takahiro Hanyu, Michitaka Kameyama: Multiple-Valued Logic-in-Memory VLSI Based on Ferroelectric Capacitor Storage and Charge Addition. ISMVL 2002: 161-

Tsukasa Ike, Takahiro Hanyu, Michitaka Kameyama: Fully Source-Coupled Logic Based Multiple-Valued VLSI. ISMVL 2002: 270-275

Tsukasa Ike, Takahiro Hanyu, Michitaka Kameyama: Dual-Rail Multiple-Valued Current-Mode VLSI with Biasing Current Sources. ISMVL 2001: 21-26

Takahiro Hanyu, Michitaka Kameyama, Katsuhiko Shimabukuro, C. Zukeran: Multiple-Valued Mask-Programmable Logic Array Using One-Transistor Universal-Literal Circuits. ISMVL 2001: 167-172

Takahiro Hanyu: Challenge of a Multiple-Valued Technology in Recent Deep-Submicron VLSI. ISMVL 2001: 241-

Takahiro Hanyu, Tsukasa Ike, Michitaka Kameyama: Low-Power Dual-Rail Multiple-Valued Current-Mode Logic Circuit Using Multiple Input-Signal Levels. ISMVL 2000: 382-

Takahiro Hanyu, Hiromitsu Kimura, Michitaka Kameyama: DRAM-Cell-Based Multiple-Valued Logic-in-Memory VLSI with Charge Addition and Charge Storage. ISMVL 2000: 423-429

Shunichi Kaeriyama, Takahiro Hanyu, Michitaka Kameyama: Arithmetic-Oriented Multiple-Valued Logic-in-Memory VLSI Based on Current-Mode Logic. ISMVL 2000: 438-

Takahiro Hanyu, Tsukasa Ike, Michitaka Kameyama: Integration of asynchronous and self-checking multiple-valued current-mode circuits based on dual-rail differential logic. PRDC 2000: 27-36

Takahiro Hanyu, Hiromitsu Kimura, Michitaka Kameyama: Multiple-Valued Content-Addressable Memory Using Metal-Ferroelectric-Semiconductor FETs. ISMVL 1999: 30-35

Takahiro Hanyu, Tsukasa Ike, Michitaka Kameyama: Self-Checking Multiple-Valued Circuit Based on Dual-Rail Current-Mode Differential Logic. ISMVL 1999: 275-279

Takahiro Saito, Takahiro Hanyu, Michitaka Kameyama: Optimal design of a current-mode deep-submicron multiple-valued integrated circuit and application. Systems and Computers in Japan 29(11): 40-47 (1998)

Takahiro Hanyu, Kaname Teranishi, Michitaka Kameyama: Design and evaluation of a digit-parallel multiple-valued content-addressable memory. Systems and Computers in Japan 29(11): 48-54 (1998)

Takahiro Hanyu, Takahiro Saito, Michitaka Kameyama: Asynchronous Multiple-Valued VLSI System Based on Dual-Rail Current-Mode Differential Logic. ISMVL 1998: 134-139

Takahiro Hanyu, Kaname Teranishi, Michitaka Kameyama: Multiple-Valued Floating-Gate-MOS Pass Logic and its Application to Logic-in-Memory VLSI. ISMVL 1998: 270-275

Takahiro Hanyu, Satoshi Kazama, Michitaka Kameyama: Low-power multiple-valued current-mode integrated circuit with current-source control and its application. ASP-DAC 1997: 413-418

Takahiro Hanyu, Manabu Arakaki, Michitaka Kameyama: One-Transistor-Cell 4-Valued Universal-Literal CAM for Cellular Logic Image Processing. ISMVL 1997: 175-

Ali Sheikholeslami, P. Glenn Gulak, Takahiro Hanyu: A Multiple-Valued Ferroelectric Content-Addressable Memory. ISMVL 1996: 74-79

Takahiro Hanyu, Manabu Arakaki, Michitaka Kameyama: Quaternary Universal-Literal CAM for Cellular Logic Image Processing. ISMVL 1996: 224-229

Xiaowei Deng, Takahiro Hanyu, Michitaka Kameyama: Quantum-Device-Oriented Multiple-Valued Logic System Based on a Super Pass Gate. IEICE Transactions 78-D(8): 951-958 (1995)

Takahiro Hanyu, Akira Mochizuki, Michitaka Kameyama: Multiple-Valued Arithmetic Integrated Circuits Based on 1.5V-Supply Dual-Rail Source-Coupled Logic. ISMVL 1995: 64-

Xiaowei Deng, Takahiro Hanyu, Michitaka Kameyama: Quantum Device Model-Based Super Pass Gate for Multiple-Valued Digital Systems. ISMVL 1995: 92-97

Takahiro Hanyu, Akira Mochizuki, Michitaka Kameyama: Multiple-Valued Current-Mode MOS Integrated Circuits Based on Dual-Rail Source-Coupled Logic. ISMVL 1994: 19-26

Satoshi Aragaki, Takahiro Hanyu, Tatsuo Higuchi: A Multiple-Valued Content-Addressable Memory Using Logic-Value Conversion and Threshold Functions. ISMVL 1993: 170-175

Takahiro Hanyu, Kouichi Takeda, Tatsuo Higuchi: Design of a Multiple-Valued Rule-Programmable Matching VLSI Chip for Real-Time Rule-Based Systems. ISMVL 1992: 274-281

Takahiro Hanyu, Yasushi Kojima, Tatsuo Higuchi: A Multiple-Valued Logic Artay VLSI Based on Two-Transistor Delta Literal Circuit and Its Application to Real-Time Reasoning Systems. ISMVL 1991: 16-23

Takahiro Hanyu, Tatsuo Higuchi: A Floating-Gate-MOS-Based Multiple-Valued Associative Memory. ISMVL 1991: 24-31

Takahiro Hanyu, Tatsuo Higuchi: Design of a High-Density Multiple-Valued Content-Addressable Memory Based on Floating-Gate MOS Devices. ISMVL 1990: 18-23