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Tetsuya Hara
1990 – 1999
- 1998
[j1]Chikako Nakanishi, Hideki Ando, Tetsuya Hara, Masao Nakaya: Software pipelining with path selection. Systems and Computers in Japan 29(9): 74-86 (1998)- 1996
[c3]Tetsuya Hara, Hideki Ando, Chikako Nakanishi, Masao Nakaya: Performance Comparison of ILP Machines with Cycle Time Evaluation. ISCA 1996: 213-224- 1995
[c2]Hideki Ando, Chikako Nakanishi, Tetsuya Hara, Masao Nakaya: Unconstrained Speculative Execution with Predicated State Buffering. ISCA 1995: 126-137- 1993
[c1]Hideki Ando, Chikako Nakanishi, Hirohisa Machida, Tetsuya Hara, Satoru Kishida, Masao Nakaya: Speculative Execution and Reducing Branch Penalty in a Parallel Issue Machine. ICCD 1993: 106-113
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last updated on 2012-12-02 21:40 CET by the dblp team



