Justin E. Harlow III

R. Iris Bahar, Dan W. Hammerstrom, Justin E. Harlow III, William H. Joyner Jr., Clifford Lau, Diana Marculescu, Alex Orailoglu, Massoud Pedram: Architectures for Silicon Nanoelectronics and Beyond. IEEE Computer 40(1): 25-33 (2007)

Venkataraman Mahalingam, N. Ranganathan, Justin E. Harlow III: A novel approach for variation aware power minimization during gate sizing. ISLPED 2006: 174-179

Justin E. Harlow III: Toward Design Technology in 2020: Trends, Issues, and Challenges. ISVLSI 2003: 3-4

Justin E. Harlow III, Franc Brglez: Design of experiments and evaluation of BDD ordering heuristics. STTT 3(2): 193-206 (2001)

Scott Davidson, Justin E. Harlow III: Guest Editors' Introduction: Benchmarking for Design and Test. IEEE Design & Test of Computers 17(3): 12-14 (2000)

Justin E. Harlow III: Overview of Popular Benchmark Sets. IEEE Design & Test of Computers 17(3): 15-17 (2000)

Justin E. Harlow III, Franc Brglez: Mirror, mirror, on the wall...is the new release any different at all? [BDDs]. ISCAS (6) 1999: 452-455

Debabrata Ghosh, Nevin Kapur, Franc Brglez, Justin E. Harlow III: Synthesis of Wiring Signature-Invariant Equivalence Class Circuit Mutants and Applications to Benchmarking. DATE 1998: 656-663

Justin E. Harlow III, Franc Brglez: Design of Experiments for Evaluation of BDD Packages Using Controlled Circuit Mutations. FMCAD 1998: 64-81

Justin E. Harlow III, Franc Brglez: Design of experiments in BDD variable ordering: lessons learned. ICCAD 1998: 646-652

Justin E. Harlow III: The open shop interactive mask design operation at harris semiconductor. DAC 1977: 331-335