Ian G. Harris

Mehryar Rahmatian, Hessam Kooti, Ian G. Harris, Elaheh Bozorgzadeh: Hardware-Assisted Detection of Malicious Software in Embedded Systems. Embedded Systems Letters 4(4): 94-97 (2012)

Ian G. Harris: Extracting design information from natural language specifications. DAC 2012: 1256-1257

Mehryar Rahmatian, Hessam Kooti, Ian G. Harris, Elaheh Bozorgzadeh: Minimization of Trojan footprint by reducing Delay/Area impact. DFT 2012: 59-62

Mehryar Rahmatian, Hessam Kooti, Ian G. Harris, Elaheh Bozorgzadeh: Adaptable intrusion detection using partial runtime reconfiguration. ICCD 2012: 147-152

Patricia S. Lee, Ian G. Harris: Test generation for subtractive specification errors. VTS 2012: 258-263

Sharon Barner, Ian G. Harris, Daniel Kroening, Orna Raz (Eds.): Hardware and Software: Verification and Testing - 6th International Haifa Verification Conference, HVC 2010, Haifa, Israel, October 4-7, 2010. Revised Selected Papers. Lecture Notes in Computer Science 6504, Springer 2011, isbn 978-3-642-19582-2

Kiran Ramineni, Shireesh Verma, Ian G. Harris: Evaluation of an efficient control-oriented coverage metric. HLDVT 2008: 153-157

Shireesh Verma, Ian G. Harris, Kiran Ramineni: Interactive presentation: Automatic generation of functional coverage models from behavioral verilog descriptions. DATE 2007: 900-905

Kiran Ramineni, Ian G. Harris, Shireesh Verma: Improving feasible interactions among multiple processes. HLDVT 2007: 11-18

Shireesh Verma, Ian G. Harris, Kiran Ramineni: Automatic generation of functional coverage models from CTL. HLDVT 2007: 159-164

Franco Fummi, Cristina Marconcini, Graziano Pravadelli, Ian G. Harris: A CLP-Based Functional ATPG for Extended FSMs. MTV 2007: 98-105

Ian G. Harris, Franco Fummi: Guest Editor's Introduction. International Journal of Parallel Programming 34(1): 1-2 (2006)

Ian G. Harris: Guest Editor's Introduction to the Special Section on Simulation-Based Design Validation. IEEE Trans. Computers 55(11): 1313-1314 (2006)

Ian G. Harris: A coverage metric for the validation of interacting processes. DATE 2006: 1019-1024

Shireesh Verma, Patricia S. Lee, Ian G. Harris: Error Detection Using Model Checking vs. Simulation. HLDVT 2006: 55-58

Franco Fummi, Ian G. Harris: Editorial. International Journal of Parallel Programming 33(6): 583-584 (2005)

Matthew W. Heath, Wayne P. Burleson, Ian G. Harris: Synchro-Tokens: A Deterministic GALS Methodology for Chip-Level Debug and Test. IEEE Trans. Computers 54(12): 1532-1546 (2005)

Ian G. Harris: Introduction. ACM Trans. Design Autom. Electr. Syst. 10(4): 587-588 (2005)

Shireesh Verma, Kiran Ramineni, Ian G. Harris: An efficient control-oriented coverage metric. ASP-DAC 2005: 317-322

Carol Stolicny, Tapio Koivukangas, Rubin A. Parekhji, Ian G. Harris, Rob Aitken: ITC 2003 panels: Part 1. IEEE Design & Test of Computers 21(2): 160-163 (2004)

Matthew W. Heath, Wayne P. Burleson, Ian G. Harris: Synchro-Tokens: Eliminating Nondeterminism to Enable Chip-Level Test of Globally-Asynchronous Locally-Synchronous SoC?s. DATE 2004: 410-415

Ian G. Harris: Fault Models and Test Generation for Hardware-Software Covalidation. IEEE Design & Test of Computers 20(4): 40-47 (2003)

Srikanth Arekapudi, Fei Xin, Jinzheng Peng, Ian G. Harris: ATPG for Timing Errors in Globally Asynchronous Locally Synchronous Systems. Journal of Circuits, Systems, and Computers 12(3): 305-332 (2003)

Qiushuang Zhang, Ian G. Harris: Partial BIST insertion to eliminate data correlation. IEEE Trans. on CAD of Integrated Circuits and Systems 22(3): 374-379 (2003)

Zhihong Zeng, Qiushuang Zhang, Ian G. Harris, Maciej J. Ciesielski: Fast Computation of Data Correlation Using BDDs. DATE 2003: 10122-10129

Emilio Gaudette, Michael Moussa, Ian G. Harris: A method for the evaluation of behavioral fault models. HLDVT 2003: 169-172

Dereck A. Fernandes, Ian G. Harris: Application of Built in Self-Test for Interconnect Testing of FPGAs. ITC 2003: 1248-1257

Ian G. Harris: The Confluence of Manufacturing Test and Design Validation. ITC 2003: 1290

Matthew W. Heath, Ian G. Harris: A Deterministic Globally Asynchronous Locally Synchronousy Microprocessor Architecture. MTV 2003: 119-

Ian G. Harris, Russell Tessier: Testing and diagnosis of interconnect faults in cluster-based FPGA architectures. IEEE Trans. on CAD of Integrated Circuits and Systems 21(11): 1337-1343 (2002)

Fei Xin, Ian G. Harris: Test generation for hardware-software covalidation using non-linear programming. HLDVT 2002: 175-180

Srikanth Arekapudi, Fei Xin, Jinzheng Peng, Ian G. Harris: Test pattern generation for timing-induced functional errors in hardware-software systems. HLDVT 2001: 83-88

Ian G. Harris: Hardware-software covalidation: fault models and test generation. HLDVT 2001: 151-156

Qiushuang Zhang, Ian G. Harris: A validation fault model for timing-induced functional errors. ITC 2001: 813-820

Ian G. Harris, Premachandran R. Menon, Russell Tessier: BIST-based delay path testing in FPGA architectures. ITC 2001: 932-938

Ian G. Harris, Russell Tessier: Interconnect testing in cluster-based FPGA architectures. DAC 2000: 49-54

Qiushuang Zhang, Ian G. Harris: A Data Flow Fault Coverage Metric for Validation of Behavioral HDL Descriptions. ICCAD 2000: 369-372

Ian G. Harris, Russell Tessier: Diagnosis of Interconnect Faults in Cluster-Based FPGA Architectures. ICCAD 2000: 472-475

Qiushuang Zhang, Ian G. Harris: A domain coverage metric for the validation of behavioral VHDL descriptions. ITC 2000: 302-308

Qiushuang Zhang, Ian G. Harris: Partial BIST insertion to eliminate data correlation. ICCAD 1999: 395-399

Ian G. Harris, Alex Orailoglu: Microarchitectural Synthesis of VLSI Designs with High Test Concurrency. DAC 1994: 206-211

Ian G. Harris, Alex Orailoglu: Fine-Grained Concurrency in Test Scheduling for Partial-Intrusion BIST. EDAC-ETC-EUROASIC 1994: 119-123

Ian G. Harris, Alex Orailoglu: SYNCBIST: SYNthesis for Concurrent Built-In-Self-Testability. ICCD 1994: 101-104

Alex Orailoglu, Ian G. Harris: Test Path Generation and Test Scheduling for Self-Testable Designs. ICCD 1993: 528-531

Ian G. Harris, Alex Orailoglu: Intertwined Scheduling, Module Selection and Allocation in Time-and-Area. ISCAS 1993: 1682-1685

P. Venkat Rangan, Walter A. Burkhard, Robert W. Rowdidge, Harrick M. Vin, John W. Lindwall, Kashun Chan, Ingvar A. Aaberg, Linda M. Yamamoto, Ian G. Harris: A Testbed for Managing Digital Video and Audio Storage. USENIX Summer 1991: 199-208