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 | 2011 | |
|---|---|---|
| c34 |      | Tomoaki Konishi, Hiroyuki Yotsuyanagi, Masaki Hashizume: Supply current testing of open defects at interconnects in 3D Ics with IEEE 1149.1 architecture. 3DIC 2011: 1-6 |
| c33 | | Widianto, Hiroyuki Yotsuyanagi, Akira Ono, Masao Takagi, Masaki Hashizume: A built-in test circuit for open defects at interconnects between dies in 3D ICs. 3DIC 2011: 1-5 |
| c32 | | Hiroyuki Yotsuyanagi, Hiroyuki Makimoto, Masaki Hashizume: A Boundary Scan Circuit with Time-to-Digital Converter for Delay Testing. Asian Test Symposium 2011: 539-544 |
| 2010 | ||
| j6 | | Hiroyuki Yotsuyanagi, Masayuki Yamamoto, Masaki Hashizume: Scan Chain Ordering to Reduce Test Data for BIST-Aided Scan Test Using Compatible Scan Flip-Flops. IEICE Transactions 93-D(1): 10-16 (2010) |
| c31 | | Masashi Ishikawa, Hiroyuki Yotsuyanagi, Masaki Hashizume: Test Data Reduction for BIST-Aided Scan Test Using Compatible Flip-Flops and Shifting Inverter Code. Asian Test Symposium 2010: 163-166 |
| c30 | | Masaki Hashizume, Kazuya Nakaminami, Hiroyuki Yotsuyanagi, Yukinori Nakajima, Kozo Kinoshita: Current-based testable design of level shifters in liquid crystal display drivers. European Test Symposium 2010: 262 |
| 2009 | ||
| c29 | | Hiroshi Takahashi, Yoshinobu Higami, Yuzo Takamatsu, Koji Yamazaki, Toshiyuki Tsutsumi, Hiroyuki Yotsuyanagi, Masaki Hashizume: New Class of Tests for Open Faults with Considering Adjacent Lines. Asian Test Symposium 2009: 301-306 |
| c28 | | Koji Yamazaki, Toshiyuki Tsutsumi, Hiroshi Takahashi, Yoshinobu Higami, Takashi Aikyo, Yuzo Takamatsu, Hiroyuki Yotsuyanagi, Masaki Hashizume: A Novel Approach for Improving the Quality of Open Fault Diagnosis. VLSI Design 2009: 85-90 |
| c27 | | Hiroyuki Yotsuyanagi, Masaki Hashizume, Toshiyuki Tsutsumi, Koji Yamazaki, Takashi Aikyo, Yoshinobu Higami, Hiroshi Takahashi, Yuzo Takamatsu: Fault Effect of Open Faults Considering Adjacent Signal Lines in a 90 nm IC. VLSI Design 2009: 91-96 |
| 2007 | ||
| c26 | | Hiroshi Takahashi, Yoshinobu Higami, Toru Kikkawa, Takashi Aikyo, Yuzo Takamatsu, Hiroyuki Yotsuyanagi, Masaki Hashizume: Test Generation and Diagnostic Test Generation for Open Faults with Considering Adjacent Lines. DFT 2007: 243-251 |
| 2006 | ||
| c25 | | Masaki Hashizume, Tomomi Nishida, Hiroyuki Yotsuyanagi, Takeomi Tamesada, Yukiya Miura: Current Testable Design of Resistor String DACs. DELTA 2006: 197-200 |
| 2005 | ||
| j5 | | Hiroyuki Yotsuyanagi, Toshimasa Kuchii, Shigeki Nishikawa, Masaki Hashizume, Kozo Kinoshita: Reducing Scan Shifts Using Configurations of Compatible and Folding Scan Trees. J. Electronic Testing 21(6): 613-620 (2005) |
| c24 | | Masaki Hashizume, Masahiro Ichimiya, Hiroyuki Yotsuyanagi, Takeomi Tamesada: Electric field for detecting open leads in CMOS logic circuits by supply current testing. ISCAS (3) 2005: 2995-2998 |
| 2004 | ||
| j4 | | Hiroyuki Yotsuyanagi, Masaki Hashizume, Takeomi Tamesada: Test Sequence Generation for Test Time Reduction of IDDQ Testing. IEICE Transactions 87-D(3): 537-543 (2004) |
| j3 | | Masaki Hashizume, Hiroyuki Yotsuyanagi, Takeomi Tamesada: Identification and Frequency Estimation of Feedback Bridging Faults Generating Logical Oscillation in CMOS Circuits. IEICE Transactions 87-D(3): 571-579 (2004) |
| j2 | | Masahiro Ichimiya, Masaki Hashizume, Hiroyuki Yotsuyanagi, Takeomi Tamesada: A test circuit for pin shorts generating oscillation in CMOS logic circuits. Systems and Computers in Japan 35(13): 10-20 (2004) |
| c23 | | Masaki Hashizume, Daisuke Yoneda, Hiroyuki Yotsuyanagi, Tetsuo Tada, Takeshi Koyama, Ikuro Morita, Takeomi Tamesada: I_DDQ Test Method Based on Wavelet Transformation for Noisy Current Measurement Environment. Asian Test Symposium 2004: 112-117 |
| c22 | | Masaki Hashizume, Tetsuo Akita, Hiroyuki Yotsuyanagi, Takeomi Tamesada: CMOS Open Fault Detection by Appearance Time of Switching Supply Current. DELTA 2004: 183-188 |
| c21 | | Isao Tsukimoto, Masaki Hashizume, Hiroyuki Yotsuyanagi, Takeomi Tamesada: Practical Fault Coverage of Supply Current Tests for Bipolar ICs. DELTA 2004: 189-194 |
| c20 | | Hiroyuki Yotsuyanagi, Toshimasa Kuchii, Shigeki Nishikawa, Masaki Hashizume, Kozo Kinoshita: On Configuring Scan Trees to Reduce Scan Shifts based on a Circuit Structure. DELTA 2004: 269-274 |
| c19 | | Daisuke Ezaki, Masaki Hashizume, Hiroyuki Yotsuyanagi, Takeomi Tamesada: A Power Supply Circuit Recycling Charge in Adiabatic Dynamic CMOS Logic Circuits. DELTA 2004: 306-311 |
| 2003 | ||
| c18 | | Hiroyuki Yotsuyanagi, Toshimasa Kuchii, Shigeki Nishikawa, Masaki Hashizume, Kozo Kinoshita: Reducing Scan Shifts Using Folding Scan Trees. Asian Test Symposium 2003: 6-11 |
| c17 | | Masaki Hashizume, Teppei Takeda, Hiroyuki Yotsuyanagi, Takeomi Tamesada, Yukiya Miura, Kozo Kinoshita: A BIST Circuit for IDDQ Tests. Asian Test Symposium 2003: 390-395 |
| 2002 | ||
| c16 | | Hiroyuki Yotsuyanagi, Masaki Hashizume, Takeomi Tamesada: Test Time Reduction for I DDQ Testing by Arranging Test Vectors. Asian Test Symposium 2002: 423-428 |
| c15 | | Hiroyuki Yotsuyanagi, Masaki Hashizume, Taisuke Iwakiri, Masahiro Ichimiya, Takeomi Tamesada: Random Pattern Testability of the Open Defect Detection Method using Application of Time-variable Electric Field. DELTA 2002: 387-391 |
| c14 | | Masaki Hashizume, Masashi Sato, Hiroyuki Yotsuyanagi, Takeomi Tamesada: Power Supply Circuit for High Speed Operation of Adiabatic Dynamic CMOS Logic Circuits. DELTA 2002: 459-461 |
| 2001 | ||
| c13 | | Hiroyuki Yotsuyanagi, Shinsuke Hata, Masaki Hashizume, Takeomi Tamesada: Sequential Redundancy Removal Using Test Generation and Multiple Unreachable States. Asian Test Symposium 2001: 23- |
| c12 | | Teppei Takeda, Masaki Hashizume, Masahiro Ichimiya, Hiroyuki Yotsuyanagi, Yukiya Miura, Kozo Kinoshita: IDDQ Sensing Technique for High Speed IDDQ Testing. Asian Test Symposium 2001: 111-116 |
| c11 | | Masaki Hashizume, Masahiro Ichimiya, Hiroyuki Yotsuyanagi, Takeomi Tamesada: CMOS Open Defect Detection Based on Supply Current in Time-Variable Electric Field and Supply Voltage Application. Asian Test Symposium 2001: 117-122 |
| c10 | | Masaki Hashizume, Masahiro Ichimiya, Hiroyuki Yotsuyanagi, Takeomi Tamesada: CMOS open defect detection by supply current test. DATE 2001: 509 |
| c9 | | Hiroyuki Yotsuyanagi, Masaki Hashizume, Taisuke Iwakiri, Masahiro Ichimiya, Takeomi Tamesada: Test Pattern for Supply Current Test of Open Defects by Applying Time-Variable Electric Field. DFT 2001: 287- |
| 2000 | ||
| c8 | | Masaki Hashizume, Hiroyuki Yotsuyanagi, Masahiro Ichimiya, Takeomi Tamesada, Masashi Takeda: High speed IDDQ test and its testability for process variation. Asian Test Symposium 2000: 344-349 |
| c7 | | Masaki Hashizume, Hiroyuki Yotsuyanagi, Takeomi Tamesada, Masashi Takeda: Testability Analysis of IDDQ Testing with Large Threshold Value. DFT 2000: 367-375 |
| 1999 | ||
| c6 | | Masaki Hashizume, Hiroyuki Yotsuyanagi, Takeomi Tamesada: Identification of Feedback Bridging Faults with Oscillation. Asian Test Symposium 1999: 25- |
| 1998 | ||
| c5 | | Masaki Hashizume, Yukiya Miura, Masahiro Ichimiya, Takeomi Tamesada, Kozo Kinoshita: A High-Speed IDDQ Sensor for Low-Voltage ICs. Asian Test Symposium 1998: 327- |
| 1997 | ||
| c4 | | Masaki Hashizume, Toshimasa Kuchii, Takeomi Tamesada: Supply Current Test for Unit-to-unit Variations of Electrical Characteristics in Gates. Asian Test Symposium 1997: 372-377 |
| 1996 | ||
| c3 | | Toshimasa Kuchii, Masaki Hashizume, Takeomi Tamesada: Algorithmic Test Generation for Supply Current Testing of TTL Combinational Circuits. Asian Test Symposium 1996: 171-176 |
| 1994 | ||
| c2 |  | Masaki Hashizume, Takeomi Tamesada, Akio Sakamoto: A Maximum Clique Derivation Algorithm for Simplification of Incompletely Specified Machines. ISCAS 1994: 193-196 |
| 1991 | ||
| j1 | | Masaki Hashizume, Takeorai Tamesada: Fault detection of ttl combinational circuits based on supply current. Systems and Computers in Japan 22(10): 18-29 (1991) |
| 1988 | ||
| c1 | | Masaki Hashizume, Takeomi Tamesada, Kazuhiro Yamada, Masaaki Kawakami: Fault Detection of Combinational Circuits Based on Supply Current. ITC 1988: 374-380 |
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