Kazumi Hatayama

Yasuo Sato, Seiji Kajihara, Tomokazu Yoneda, Kazumi Hatayama, Michiko Inoue, Yukiya Miura, Satosni Untake, Takumi Hasegawa, Motoyuki Sato, Kotaro Shimamura: DART: Dependable VLSI test architecture and its implementation. ITC 2012: 1-10

Yuta Yamato, Tomokazu Yoneda, Kazumi Hatayama, Michiko Inoue: A fast and accurate per-cell dynamic IR-drop estimation method for at-speed scan test pattern validation. ITC 2012: 1-8

Kohei Miyase, Kenji Noda, Hideaki Ito, Kazumi Hatayama, Takashi Aikyo, Yuta Yamato, Hiroshi Furukawa, Xiaoqing Wen, Seiji Kajihara: Distribution-Controlled X-Identification for Effective Reduction of Launch-Induced IR-Drop in At-Speed Scan Testing. IEICE Transactions 94-D(6): 1216-1226 (2011)

Kazumi Hatayama, Tsuyoshi Shinogi: Foreword. IEICE Transactions 93-D(1): 1 (2010)

Kohei Miyase, Xiaoqing Wen, Seiji Kajihara, Yuta Yamato, Atsushi Takashima, Hiroshi Furukawa, Kenji Noda, Hideaki Ito, Kazumi Hatayama, Takashi Aikyo, Kewal K. Saluja: A Study of Capture-Safe Test Generation Flow for At-Speed Testing. IEICE Transactions 93-A(7): 1309-1318 (2010)

Takumi Uezono, Tomoyuki Takahashi, Michihiro Shintani, Kazumi Hatayama, Kazuya Masu, Hiroyuki Ochi, Takashi Sato: Scan based process parameter estimation through path-delay inequalities. ISCAS 2010: 3553-3556

Takumi Uezono, Tomoyuki Takahashi, Michihiro Shintani, Kazumi Hatayama, Kazuya Masu, Hiroyuki Ochi, Takashi Sato: Path clustering for adaptive test. VTS 2010: 15-20

Michihiro Shintani, Takumi Uezono, Tomoyuki Takahashi, Hiroyuki Ueyama, Takashi Sato, Kazumi Hatayama, Takashi Aikyo, Kazuya Masu: An Adaptive Test for Parametric Faults Based on Statistical Timing Information. Asian Test Symposium 2009: 151-156

Kohei Miyase, Yuta Yamato, Kenji Noda, Hideaki Ito, Kazumi Hatayama, Takashi Aikyo, Xiaoqing Wen, Seiji Kajihara: A novel post-ATPG IR-drop reduction scheme for at-speed scan testing in broadcast-scan-based test compression environment. ICCAD 2009: 97-104

Masayuki Arai, Akifumi Suto, Kazuhiko Iwasaki, Katsuyuki Nakano, Michihiro Shintani, Kazumi Hatayama, Takashi Aikyo: Small Delay Fault Model for Intra-Gate Resistive Open Defects. VTS 2009: 27-32

X. Wen, Kohei Miyase, Seiji Kajihara, Hiroshi Furukawa, Yuta Yamato, Atsushi Takashima, Kenji Noda, H. Ito, Kazumi Hatayama, Takashi Aikyo, Kewal K. Saluja: A Capture-Safe Test Generation Scheme for At-Speed Scan Testing. European Test Symposium 2008: 55-60

Kohei Miyase, Kenji Noda, Hideaki Ito, Kazumi Hatayama, Takashi Aikyo, Yuta Yamato, Hiroshi Furukawa, Xiaoqing Wen, Seiji Kajihara: Effective IR-drop reduction in at-speed scan testing using Distribution-Controlling X-Identification. ICCAD 2008: 52-58

Seiji Kajihara, Shohei Morishima, Masahiro Yamamoto, Xiaoqing Wen, Masayasu Fukunaga, Kazumi Hatayama, Takashi Aikyo: Estimation of delay test quality and its application to test generation. ICCAD 2007: 413-417

Kazumi Hatayama: Session Abstract. VTS 2006: 200-201

Kazumi Hatayama, Rochit Rajsuman: Opportunities with the open architecture test system. ASP-DAC 2004: 334

Yasuo Sato, Motoyuki Sato, Koki Tsutsumida, Masatoshi Kawashima, Kazumi Hatayama, Kazuyuki Nomoto: DFT timing design methodology for at-speed BIST. ASP-DAC 2003: 763-768

Kazumi Hatayama, Michinobu Nakao, Yasuo Sato: At-Speed Built-in Test for Logic Circuits with Multiple Clocks. Asian Test Symposium 2002: 292-297

Kazumi Hatayama, Michinobu Nakao, Yoshikazu Kiyoshige, Koichiro Natsume, Yasuo Sato, Takaharu Nagumo: Application of High-Quality Built-In Test to Industrial Designs. ITC 2002: 1003-1012

Michinobu Nakao, Yoshikazu Kiyoshige, Kazumi Hatayama, Yasuo Sato, Takaharu Nagumo: Test Generation for Multiple-Threshold Gate-Delay Fault Model. Asian Test Symposium 2001: 244-

Michinobu Nakao, Seiji Kobayashi, Kazumi Hatayama, Kazuhiko Iijima, Seiji Terada: Low overhead test point insertion for scan-based BIST. ITC 1999: 348-357

Kazumi Hatayama, Mitsuji Ikeda, Masahiro Takakura, Satoshi Uchiyama, Yoriyuki Sakamoto: Application of a Design for Delay Testability Approach to High Speed Logic LSIs. Asian Test Symposium 1997: 112-115

Michinobu Nakao, Kazumi Hatayama, Isao Higashi: Accelerated Test Points Selection Method for Scan-Based BIST. Asian Test Symposium 1997: 359-

Kazumi Hatayama, Kazunori Hikone, T. Miyazaki, H. Yamada: A practical approach to instruction-based test generation for functional modules of VLSI processors. VTS 1997: 17-23

Hiroshi Date, Michinobu Nakao, Kazumi Hatayama: A parallel sequential test generation system DESCARTES based on real-valued logic simulation. Asian Test Symposium 1995: 252-258

Kazunori Hikone, Mitsuji Ikeda, Kazumi Hatayama, Terumine Hayashi: Sequential circuit test generation by real number simulation. Systems and Computers in Japan 24(9): 64-75 (1993)

Kazumi Hatayama, Kazunori Hikone, Mitsuji Ikeda, Terumine Hayashi: Sequential Test Generation Based on Real-Value Logic. ITC 1992: 41-48

Kazumi Hatayama, Mitsuji Ikeda, Terumine Hayashi, Masahiro Takakura, Kuniaki Kishida, Shun Ishiyama: Enhanced Delay Test Generator for High-Speed Logic LSIs. ITC 1989: 161-165