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 | 2009 | |
|---|---|---|
| c21 |      | Haruhiko Takase, Masaru Fujita, Hiroharu Kawanaka, Shinji Tsuruoka, Hidehiko Kita, Terumine Hayashi: Obstacle to training SpikeProp networks - Cause of surges in training process -. IJCNN 2009: 3062-3066 |
| 2008 | ||
| c20 | | Masaru Fujita, Haruhiko Takase, Hidehiko Kita, Terumine Hayashi: Shape of error surfaces in SpikeProp. IJCNN 2008: 840-844 |
| 2007 | ||
| c19 | | Kazutaka Noro, Haruhiko Takase, Hidehiko Kita, Terumine Hayashi, Naoki Morita: Descriptive Answer Clustering System for Immediate Feedback. ICCE 2007: 37-40 |
| c18 | | Haruhiko Takase, Masahiko Masahiko, Hidehiko Kita, Terumine Hayashi: Enhancing both generalization and fault tolerance of multilayer neural networks. IJCNN 2007: 1429-1433 |
| 2006 | ||
| c17 | | Haruhiko Takase, Hidehiko Kita, Terumine Hayashi: Fault tolerant training algorithm for multi-layer neural networks focused on hidden unit activities. IJCNN 2006: 1540-1545 |
| 2005 | ||
| j4 | | Terumine Hayashi, Haruna Yoshioka, Tsuyoshi Shinogi, Hidehiko Kita, Haruhiko Takase: On Test Data Compression Using Selective Don't-Care Identification. J. Comput. Sci. Technol. 20(2): 210-215 (2005) |
| c16 | | Tsuyoshi Shinogi, Hiroyuki Yamada, Terumine Hayashi, Shinji Tsuruoka, Tomohiro Yoshikawa: A Test Cost Reduction Method by Test Response and Test Vector Overlapping for Full-Scan Test Architecture. Asian Test Symposium 2005: 366-371 |
| 2004 | ||
| c15 | | Terumine Hayashi, Haruna Yoshioka, Tsuyoshi Shinogi, Hidehiko Kita, Haruhiko Takase: Test data compression technique using selective don't-care identification. ASP-DAC 2004: 230-233 |
| 2003 | ||
| c14 | | Tsuyoshi Shinogi, Yuki Yamada, Terumine Hayashi, Tomohiro Yoshikawa, Shinji Tsuruoka: Between-Core Vector Overlapping for Test Cost Reduction in Core Testing. Asian Test Symposium 2003: 268-273 |
| 2001 | ||
| j3 | | Junzhi Sang, Tsuyoshi Shinogi, Haruhiko Takase, Hidehiko Kita, Terumine Hayashi: An enhanced fault model for high defect coverage. Systems and Computers in Japan 32(6): 36-44 (2001) |
| c13 | | Tsuyoshi Shinogi, Tomokazu Kanbayashi, Tomohiro Yoshikawa, Shinji Tsuruoka, Terumine Hayashi: Faulty Resistance Sectioning Technique for Resistive Bridging Fault ATPG Systems. Asian Test Symposium 2001: 76-81 |
| 2000 | ||
| c12 | | Tsuyoshi Shinogi, Masahiro Ushio, Terumine Hayashi: Cyclic greedy generation method for limited number of IDDQ tests. Asian Test Symposium 2000: 362- |
| c11 | | Haruhiko Takase, Tsuyoshi Shinogi, Terumine Hayashi, Hidehiko Kita: Evaluation Function for Fault Tolerant Multi-Layer Neural Networks. IJCNN (3) 2000: 521-526 |
| 1999 | ||
| j2 | | Tsuyoshi Shinogi, Terumine Hayashi, Kazuo Taki: Test generation for stuck-on faults in pass-transistor logic SPL and implementation of DFT circuits. Systems and Computers in Japan 30(7): 55-68 (1999) |
| c10 | | Kai Zhang, Tsuyoshi Shinogi, Haruhiko Takase, Terumine Hayashi: A Method for Evaluating Upper Bound of Simultaneous Switching Gates Using Circuit Partition. ASP-DAC 1999: 291-294 |
| c9 | | Tsuyoshi Shinogi, Terumine Hayashi: A Parallel Generation System of Compact IDDQ Test Sets for Large Combinational Circuits. Asian Test Symposium 1999: 164- |
| 1998 | ||
| c8 | | Junzhi Sang, Tsuyoshi Shinogi, Haruhiko Takase, Terumine Hayashi: On a Logical Fault Model H1SGLF for Enhancing Defect Coverage. Asian Test Symposium 1998: 102-107 |
| c7 | | Tsuyoshi Shinogi, Terumine Hayashi: A Simple and Efficient Method for Generating Compact IDDQ Test Set for Bridging Fault. VTS 1998: 112-117 |
| 1997 | ||
| c6 | | Kai Zhang, Haruhiko Takase, Terumine Hayashi, Hidehiko Kita: An enhanced iterative improvement method for evaluating the maximum number of simultaneous switching gates for combinational circuits. ASP-DAC 1997: 107-112 |
| c5 | | Tsuyoshi Shinogi, Terumine Hayashi, Kazuo Taki: Test Generation for Stuck-On Faults in BDD-Based Pass-Transistor Logic SPL. Asian Test Symposium 1997: 16-21 |
| 1993 | ||
| j1 | | Kazunori Hikone, Mitsuji Ikeda, Kazumi Hatayama, Terumine Hayashi: Sequential circuit test generation by real number simulation. Systems and Computers in Japan 24(9): 64-75 (1993) |
| 1992 | ||
| c4 | | Kazumi Hatayama, Kazunori Hikone, Mitsuji Ikeda, Terumine Hayashi: Sequential Test Generation Based on Real-Value Logic. ITC 1992: 41-48 |
| 1991 | ||
| c3 |  | Yutaka Sekiyama, Yasuyuki Fujihara, Terumine Hayashi, Mitsuho Seki, Jiro Kusuhara, Kazuhiko Iijima, Masahiro Takakura, Koji Fukatani: Timing-Oriented Routers for PCB Layout Design of High-Performance Computers. ICCAD 1991: 332-335 |
| 1989 | ||
| c2 | | Kazumi Hatayama, Mitsuji Ikeda, Terumine Hayashi, Masahiro Takakura, Kuniaki Kishida, Shun Ishiyama: Enhanced Delay Test Generator for High-Speed Logic LSIs. ITC 1989: 161-165 |
| 1986 | ||
| c1 | | Kuniaki Kishida, F. Shirotori, Y. Ikemoto, Shun Ishiyama, Terumine Hayashi: A delay test system for high speed logic LSI's. DAC 1986: 786-790 |
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