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 | 2012 | |
|---|---|---|
| j5 |      | Apala Guha, Kim M. Hazelwood, Mary Lou Soffa: Memory optimization of dynamic binary translators for embedded systems. TACO 9(3): 22 (2012) |
| c27 | | Chris Gregg, Luther A. Tychonievich, James P. Cohoon, Kim M. Hazelwood: EcoSim: a language and experience teaching parallel programming in elementary school. SIGCSE 2012: 51-56 |
| 2011 | ||
| b1 | | Kim M. Hazelwood: Dynamic Binary Modification: Tools, Techniques, and Applications. Synthesis Lectures on Computer Architecture, Morgan & Claypool Publishers 2011 |
| c26 | | Perhaad Mistry, Chris Gregg, Norman Rubin, David R. Kaeli, Kim M. Hazelwood: Analyzing program flow within a many-kernel OpenCL application. GPGPU 2011: 10 |
| c25 | | Kim M. Hazelwood: Process-level virtualization for runtime adaptation of embedded software. DAC 2011: 895-900 |
| c24 | | Dan Upton, Kim M. Hazelwood: Finding cool code: An analysis of source-level causes of temperature effects. ISPASS 2011: 117-118 |
| c23 | | Michelle McDaniel, Kim M. Hazelwood: Performance characterization of mobile-class nodes: Why fewer bits is better. ISPASS 2011: 131-132 |
| c22 | | Chris Gregg, Kim M. Hazelwood: Where is the data? Why you cannot debate CPU vs. GPU performance without the answer. ISPASS 2011: 134-144 |
| 2010 | ||
| j4 | | Moshe Bach, Mark Charney, Robert Cohn, Elena Demikhovsky, Tevi Devor, Kim M. Hazelwood, Aamer Jaleel, Chi-Keung Luk, Gail Lyons, Harish Patil, Ady Tal: Analyzing Parallel Programs with Pin. IEEE Computer 43(3): 34-41 (2010) |
| j3 | | Vijay Janapa Reddi, Simone Campanoni, Meeta Sharma Gupta, Michael D. Smith, Gu-Yeon Wei, David Brooks, Kim M. Hazelwood: Eliminating voltage emergencies via software-guided code transformations. TACO 7(2) (2010) |
| c21 | | Apala Guha, Kim M. Hazelwood, Mary Lou Soffa: Balancing memory and performance through selective flushing of software code caches. CASES 2010: 1-10 |
| c20 | | Alex Skaletsky, Tevi Devor, Nadav Chachmon, Robert S. Cohn, Kim M. Hazelwood, Vladimir Vladimirov, Moshe Bach: Dynamic program analysis of Microsoft Windows applications. ISPASS 2010: 2-12 |
| c19 | | |
| c18 | | Apala Guha, Kim M. Hazelwood, Mary Lou Soffa: DBT path selection for holistic memory efficiency and performance. VEE 2010: 145-156 |
| e1 |  | Andreas Moshovos, J. Gregory Steffan, Kim M. Hazelwood, David R. Kaeli (Eds.): Proceedings of the CGO 2010, The 8th International Symposium on Code Generation and Optimization, Toronto, Ontario, Canada, April 24-28, 2010. ACM 2010, isbn 978-1-60558-635-9 |
| 2009 | ||
| j2 | | Kim M. Hazelwood, Mohamed Zahran: Challenges and opportunities at all levels: interactions among operating systems, compilers, and multicore processors. Operating Systems Review 43(2): 3-4 (2009) |
| c17 | | Kim M. Hazelwood, Greg Lueck, Robert Cohn: Scalable support for multithreaded applications on dynamic binary instrumentation systems. ISMM 2009: 20-29 |
| c16 | | Daniel W. Williams, Aprotim Sanyal, Dan Upton, Jason Mars, Sudeep Ghosh, Kim M. Hazelwood: A cross-layer approach to heterogeneity and reliability. MEMOCODE 2009: 88-97 |
| 2008 | ||
| c15 | | Arkaitz Ruiz-Alvarez, Kim M. Hazelwood: Evaluating the impact of dynamic binary translation systems on hardware cache performance. IISWC 2008: 131-140 |
| c14 | | |
| 2007 | ||
| c13 | | Steven Wallace, Kim M. Hazelwood: SuperPin: Parallelizing Dynamic Instrumentation for Real-Time Performance. CGO 2007: 209-220 |
| c12 | | Apala Guha, Kim M. Hazelwood, Mary Lou Soffa: Reducing Exit Stub Memory Consumption in Code Caches. HiPEAC 2007: 87-101 |
| c11 | | Apala Guha, Jason Hiser, Naveen Kumar, Jing Yang, Min Zhao, Shukang Zhou, Bruce R. Childers, Jack W. Davidson, Kim M. Hazelwood, Mary Lou Soffa: Virtual Execution Environments: Support and Tools. IPDPS 2007: 1-6 |
| 2006 | ||
| j1 | | Kim M. Hazelwood, Michael D. Smith: Managing bounded code caches in dynamic binary optimization systems. TACO 3(3): 263-294 (2006) |
| c10 | | Kim M. Hazelwood, Artur Klauser: A dynamic binary instrumentation engine for the ARM architecture. CASES 2006: 261-270 |
| c9 | | Kim M. Hazelwood, Robert S. Cohn: A Cross-Architectural Interface for Code Cache Manipulation. CGO 2006: 17-27 |
| 2005 | ||
| c8 | | David Hiniker, Kim M. Hazelwood, Michael D. Smith: Improving Region Selection in Dynamic Optimization Systems. MICRO 2005: 141-154 |
| c7 | | Chi-Keung Luk, Robert S. Cohn, Robert Muth, Harish Patil, Artur Klauser, P. Geoffrey Lowney, Steven Wallace, Vijay Janapa Reddi, Kim M. Hazelwood: Pin: building customized program analysis tools with dynamic instrumentation. PLDI 2005: 190-200 |
| 2004 | ||
| c6 | | Kim M. Hazelwood, James E. Smith: Exploring Code Cache Eviction Granularities in Dynamic Optimization Systems. CGO 2004: 89-99 |
| c5 | | Kim M. Hazelwood, David Brooks: Eliminating voltage emergencies via microarchitectural voltage control feedback and dynamic optimization. ISLPED 2004: 326-331 |
| 2003 | ||
| c4 | | |
| c3 | | Kim M. Hazelwood, Michael D. Smith: Generational Cache Management of Code Traces in Dynamic Optimization Systems. MICRO 2003: 169-179 |
| 2002 | ||
| c2 | | Kim M. Hazelwood, Michael D. Smith: Code Cache Management Schemes for Dynamic Optimizers. Interaction between Compilers and Computer Architectures 2002: 102-110 |
| 2000 | ||
| c1 | | Kim M. Hazelwood, Thomas M. Conte: A Lightweight Algorithm for Dynamic If-Conversion during Dynamic Optimization. IEEE PACT 2000: 71-80 |
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