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 | 2010 | |
|---|---|---|
| c7 |      | Stephan Henzler: Digitalization of mixed-signal functionality in nanometer technologies. ICCAD 2010: 252-255 |
| 2008 | ||
| j1 | | Stephan Henzler, Siegmar Koeppe: Design and Application of Power Optimized High-Speed CMOS Frequency Dividers. IEEE Trans. VLSI Syst. 16(11): 1513-1520 (2008) |
| 2006 | ||
| c6 | | Stephan Henzler, Siegmar Koeppe: High-speed low-power frequency divider with intrinsic phase rotator. ISLPED 2006: 286-291 |
| 2005 | ||
| c5 | | Stephan Henzler, Thomas Nirschl, Matthias Eireiner, Ettore Amirante, Doris Schmitt-Landsiedel: Making adiabatic circuits attractive for todays VLSI industry by multi-mode operation-adiabatic mode circuits. Conf. Computing Frontiers 2005: 414-420 |
| c4 | | Philip Teichmann, Jürgen Fischer, Stephan Henzler, Ettore Amirante, Doris Schmitt-Landsiedel: Power-Clock Gating in Adiabatic Logic Circuits. PATMOS 2005: 638-646 |
| 2004 | ||
| c3 | | Stephan Henzler, Georg Georgakos, Jörg Berthold, Doris Schmitt-Landsiedel: Single Supply Voltage High-Speed Semi-dynamic Level-Converting Flip-Flop with Low Power and Area Consumption. PATMOS 2004: 392-401 |
| c2 | | Stephan Henzler, Georg Georgakos, Jörg Berthold, Doris Schmitt-Landsiedel: Two Level Compact Simulation Methodology for Timing Analysis of Power-Switched Circuits. PATMOS 2004: 789-798 |
| 2003 | ||
| c1 |  | Stephan Henzler, Markus Koban, Doris Schmitt-Landsiedel, Jörg Berthold, Georg Georgakos: Design Aspects and Technological Scaling Limits of ZigZag Circuit Block Switch-Off Schemes. VLSI-SOC 2003: 246-251 |
| 1 | Ettore Amirante | |
| 2 | Jörg Berthold | |
| 3 | Matthias Eireiner | |
| 4 | Jürgen Fischer | |
| 5 | Georg Georgakos | |
| 6 | Markus Koban | |
| 7 | Siegmar Koeppe | |
| 8 | Thomas Nirschl | |
| 9 | Doris Schmitt-Landsiedel | |
| 10 | Philip Teichmann |
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