Osamu Hirabayashi Coauthor index pubzone.org

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c5Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XML
Fumihiko Tachibana, Osamu Hirabayashi, Yasuhisa Takeyama, Miyako Shizuno, Atsushi Kawasumi, Keiichi Kushida, Azuma Suzuki, Yusuke Niki, Shinichi Sasaki, Tomoaki Yabe, Yasuo Unekawa: A 27% active and 85% standby power reduction in dual-power-supply SRAM using BL power calculator and digitally controllable retention circuit. ISSCC 2013: 320-321
2011
j2Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XML
Yusuke Niki, Atsushi Kawasumi, Azuma Suzuki, Yasuhisa Takeyama, Osamu Hirabayashi, Keiichi Kushida, Fumihiko Tachibana, Yuki Fujimura, Tomoaki Yabe: A Digitized Replica Bitline Delay Technique for Random-Variation-Tolerant Timing Generation of SRAM Sense Amplifiers. J. Solid-State Circuits 46(11): 2545-2551 (2011)
2010
j1Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XML
Atsushi Kawasumi, Yasuhisa Takeyama, Osamu Hirabayashi, Keiichi Kushida, Yuki Fujimura, Tomoaki Yabe: A Low-Supply-Voltage-Operation SRAM With HCI Trimmed Sense Amplifiers. J. Solid-State Circuits 45(11): 2341-2347 (2010)
c4Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XML
Yuki Fujimura, Osamu Hirabayashi, Takahiko Sasaki, Azuma Suzuki, Atsushi Kawasumi, Yasuhisa Takeyama, Keiichi Kushida, Gou Fukano, Akira Katayama, Yusuke Niki, Tomoaki Yabe: A configurable SRAM with constant-negative-level write buffer for low-voltage operation with 0.149µm2 cell in 32nm high-k metal-gate CMOS. ISSCC 2010: 348-349
2009
c3Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XML
Osamu Hirabayashi, Atsushi Kawasumi, Azuma Suzuki, Yasuhisa Takeyama, Keiichi Kushida, Takahiko Sasaki, Akira Katayama, Gou Fukano, Yuki Fujimura, Takaaki Nakazato, Yasushi Shizuki, Natsuki Kushiyama, Tomoaki Yabe: A process-variation-tolerant dual-power-supply SRAM with 0.179µm2 Cell in 40nm CMOS using level-programmable wordline driver. ISSCC 2009: 458-459
2008
c2Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XML
Akira Katayama, Tomoaki Yabe, Osamu Hirabayashi, Yasuhisa Takeyama, Keiichi Kushida, Takahiko Sasaki, Nobuaki Otsuka: Direct Cell-Stability Test Techniques for an SRAM Macro with Asymmetric Cell-Bias-Voltage Modulation. ITC 2008: 1-7
2002
c1Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XML
Osamu Hirabayashi, Azuma Suzuki, Tomoaki Yabe, Atsushi Kawasumi, Yasuhisa Takeyama, Keiichi Kushida, A. Tohata, Nobuaki Otsuka: DFT Techniques for Wafer-Level At-Speed Testing of High-Speed SRAMs. ITC 2002: 164-169

Coauthor Index

1Yuki Fujimura
[j2] [j1] [c4] [c3]
2Gou Fukano
[c4] [c3]
3Akira Katayama
[c4] [c3] [c2]
4Atsushi Kawasumi
[c5] [j2] [j1] [c4] [c3] [c1]
5Keiichi Kushida
[c5] [j2] [j1] [c4] [c3] [c2] [c1]
6Natsuki Kushiyama
[c3]
7Takaaki Nakazato
[c3]
8Yusuke Niki
[c5] [j2] [c4]
9Nobuaki Otsuka
[c2] [c1]
10Shinichi Sasaki
[c5]
11Takahiko Sasaki
[c4] [c3] [c2]
12Yasushi Shizuki
[c3]
13Miyako Shizuno
[c5]
14Azuma Suzuki
[c5] [j2] [c4] [c3] [c1]
15Fumihiko Tachibana
[c5] [j2]
16Yasuhisa Takeyama
[c5] [j2] [j1] [c4] [c3] [c2] [c1]
17A. Tohata
[c1]
18Yasuo Unekawa
[c5]
19Tomoaki Yabe
[c5] [j2] [j1] [c4] [c3] [c2] [c1]
Last update Tue May 21 19:45:19 2013 CET by the DBLP TeamThis material is Open Data Data released under the ODC-BY 1.0 license — See also our legal information page