Tetsuya Hirose

Igors Homjakovs, Masanori Hashimoto, Tetsuya Hirose, Takao Onoye: Signal-Dependent Analog-to-Digital Conversion Based on MINIMAX Sampling. IEICE Transactions 96-A(2): 459-468 (2013)

Yuji Osaki, Tetsuya Hirose, Nobutaka Kuroki, Masahiro Numa: A Low-Power Level Shifter With Logic Error Correction for Extremely Low-Voltage Digital CMOS LSIs. J. Solid-State Circuits 47(7): 1776-1783 (2012)

Yumiko Tsuruya, Tetsuya Hirose, Yuji Osaki, Nobutaka Kuroki, Masahiro Numa, Osamu Kobayashi: A nano-watt power CMOS amplifier with adaptive biasing for power-aware analog LSIs. ESSCIRC 2012: 69-72

Yuji Osaki, Tetsuya Hirose, Kei Matsumoto, Nobutaka Kuroki, Masahiro Numa: Robust Subthreshold CMOS Digital Circuit Design with On-Chip Adaptive Supply Voltage Scaling Technique. IEICE Transactions 94-C(1): 80-88 (2011)

Kei Matsumoto, Tetsuya Hirose, Yuji Osaki, Nobutaka Kuroki, Masahiro Numa: Subthreshold SRAM with Write Assist Technique Using On-Chip Threshold Voltage Monitoring Circuit. IEICE Transactions 94-C(6): 1042-1048 (2011)

Yuji Osaki, Tetsuya Hirose, Nobutaka Kuroki, Masahiro Numa: A 95-nA, 523ppm/°C, 0.6-μW CMOS current reference circuit with subthreshold MOS resistor ladder. ASP-DAC 2011: 113-114

Yuji Osaki, Tetsuya Hirose, Nobutaka Kuroki, Masahiro Numa: A level shifter with logic error correction circuit for extremely low-voltage digital CMOS LSIs. ESSCIRC 2011: 199-202

Yusuke Tsugita, Ken Ueno, Tetsuya Hirose, Tetsuya Asai, Yoshihito Amemiya: An On-Chip PVT Compensation Technique with Current Monitoring Circuit for Low-Voltage CMOS Digital LSIs. IEICE Transactions 93-C(6): 835-841 (2010)

Kosuke Shioki, Narumi Okada, Kosuke Watanabe, Tetsuya Hirose, Nobutaka Kuroki, Masahiro Numa: An Error Diagnosis Technique Based on Clustering of Elements. IEICE Transactions 93-A(12): 2490-2496 (2010)

Ken Ueno, Tetsuya Hirose, Tetsuya Asai, Yoshihito Amemiya: A 1-muhboxW 600- hboxppm/^circhboxC Current Reference Circuit Consisting of Subthreshold CMOS Circuits. IEEE Trans. on Circuits and Systems 57-II(9): 681-685 (2010)

Shingo Chikamatsu, Tomohiro Nakaya, Masakazu Kouda, Nobutaka Kuroki, Tetsuya Hirose, Masahiro Numa: Super-resolution technique for thermography with dual-camera system. ISCAS 2010: 1895-1898

Taichi Ogawa, Tetsuya Hirose, Tetsuya Asai, Yoshihito Amemiya: Threshold-Logic Devices Consisting of Subthreshold CMOS Circuits. IEICE Transactions 92-A(2): 436-442 (2009)

Ken Ueno, Tetsuya Hirose, Tetsuya Asai, Yoshihito Amemiya: Low-Voltage Process-Compensated VCO with On-Chip Process Monitoring and Body-Biasing Circuit Techniques. IEICE Transactions 92-A(12): 3079-3081 (2009)

Kosuke Shioki, Narumi Okada, Toshiro Ishihara, Tetsuya Hirose, Nobutaka Kuroki, Masahiro Numa: An Error Diagnosis Technique Based on Location Sets to Rectify Subcircuits. IEICE Transactions 92-A(12): 3136-3142 (2009)

Ken Ueno, Tetsuya Hirose, Tetsuya Asai, Yoshihito Amemiya: A 300 nW, 7 ppm/degreeC CMOS voltage reference circuit based on subthreshold MOSFETs. ASP-DAC 2009: 95-96

Yusuke Tsugita, Ken Ueno, Tetsuya Asai, Yoshihito Amemiya, Tetsuya Hirose: On-chip PVT Compensation Techniques for Low-voltage CMOS Digital LSIs. ISCAS 2009: 1565-1568

Akira Utagawa, Tetsuya Asai, Tetsuya Hirose, Yoshihito Amemiya: Noise-Induced Synchronization among Sub-RF CMOS Analog Oscillators for Skew-Free Clock Distribution. IEICE Transactions 91-A(9): 2475-2481 (2008)

Kazuhito Yamada, Tetsuya Asai, Tetsuya Hirose, Yoshihito Amemiya: On Digital LSI Circuits Exploiting Collision-Based Fusion Gates. IJUC 4(1): 45-59 (2008)

Akira Utagawa, Tetsuya Asai, Tetsuya Hirose, Yoshihito Amemiya: An Inhibitory Neural-Network Circuit Exhibiting Noise Shaping with Subthreshold MOS Neuron Circuits. IEICE Transactions 90-A(10): 2108-2115 (2007)

Motoyoshi Takahashi, Tetsuya Asai, Tetsuya Hirose, Yoshihito Amemiya: A CMOS Reaction-diffusion Device Using Minority-Carrier Diffusion in Semiconductors. I. J. Bifurcation and Chaos 17(5): 1713-1719 (2007)

Kazuki Nakada, Tetsuya Asai, Tetsuya Hirose, Hatsuo Hayashi, Yoshihito Amemiya: A subthreshold CMOS circuit for a piecewise linear neuromorphic oscillator with current-mode low-pass filters. Neurocomputing 71(1-3): 3-12 (2007)

Gessyca Maria Tovar, Eric Shun Fukuda, Tetsuya Asai, Tetsuya Hirose, Yoshihito Amemiya: Analog CMOS Circuits Implementing Neural Segmentation Model Based on Symmetric STDP Learning. ICONIP (2) 2007: 117-126

Gessyca Maria Tovar, Eric Shun Fukuda, Tetsuya Asai, Tetsuya Hirose, Yoshihito Amemiya: Neuromorphic CMOS Circuits implementing a Novel Neural Segmentation Model based on Symmetric STDP Learning. IJCNN 2007: 897-901

Ken Ueno, Tetsuya Hirose, Tetsuya Asai, Yoshihito Amemiya: Floating millivolt reference for PTAT current generation in Subthreshold MOS LSIs. ISCAS 2007: 3748-3751

Ken Ueno, Tetsuya Hirose, Tetsuya Asai, Yoshihito Amemiya: A CMOS Watchdog Sensor for Certifying the Quality of Various Perishables with a Wider Activation Energy. IEICE Transactions 89-A(4): 902-907 (2006)

Tetsuya Asai, Taishi Kamiya, Tetsuya Hirose, Yoshihito Amemiya: A subthreshold Analog MOS Circuit for Lotka-volterra Chaotic oscillator. I. J. Bifurcation and Chaos 16(1): 207-212 (2006)

Sungwoo Cha, Tetsuya Hirose, Masaki Haruoka, Toshimasa Matsuoka, Kenji Taniguchi: A CMOS IF Variable Gain Amplifier with Exponential Gain Control. IEICE Transactions 88-A(2): 410-415 (2005)

Tetsuya Hirose, Toshimasa Matsuoka, Kenji Taniguchi, Tetsuya Asai, Yoshihito Amemiya: Ultralow-Power Current Reference Circuit with Low Temperature Dependence. IEICE Transactions 88-C(6): 1142-1147 (2005)

Tetsuya Asai, Masayuki Ikebe, Tetsuya Hirose, Yoshihito Amemiya: A quadrilateral-object composer for binary images with reaction-diffusion cellular automata. Parallel Algorithms Appl. 20(1): 57-67 (2005)

Yusuke Kanazawa, Tetsuya Asai, Tetsuya Hirose, Yoshihito Amemiya: A MOS circuit for bursting neural oscillators with excitable oregonators. IEICE Electronic Express 1(4): 73-76 (2004)

Masayuki Furuhashi, Tetsuya Hirose, Hiroshi Tsuji, Masayuki Tachi, Kenji Taniguchi: Atomic configuration of boron pile-up at the Si/SiO2 interface. IEICE Electronic Express 1(6): 126-130 (2004)

Hiroshi Matsubara, Tetsuya Asai, Tetsuya Hirose, Yoshihito Amemiya: Reaction-diffusion chip implementing excitable lattices with multiple-valued cellular automata. IEICE Electronic Express 1(9): 248-252 (2004)

Takeo Hosomi, Yasushi Kanoh, Masaaki Nakamura, Tetsuya Hirose: A DSM Architecture for a Parallel Computer Cenju-4. HPCA 2000: 287-298

Yasushi Kanoh, Masaaki Nakamura, Tetsuya Hirose, Takeo Hosomi, Hirokazu Takayama, Toshiyuki Nakata: Message Passing Communication in a Parallel Computer Cenju-4. ISHPC 1999: 55-70

Tsutomu Maruyama, Yasushi Kanoh, Tetsuya Hirose, Kazuhiro Muramatsu, Toshiyuki Nakata, Yoshihiro Asano, Yu Inamura: Architecture of a parallel machine: Cenju-3. Systems and Computers in Japan 26(14): 26-36 (1995)

Tsutomu Maruyama, Tetsuya Hirose, Akihiko Konagaya: A Fine-Grained Parallel Genetic Algorithm for Distributed Parallel Systems. ICGA 1993: 184-190