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 | 2012 | |
|---|---|---|
| j3 |      | Kuan-Hsien Ho, Jie-Hong Roland Jiang, Yao-Wen Chang: TRECO: Dynamic Technology Remapping for Timing Engineering Change Orders. IEEE Trans. on CAD of Integrated Circuits and Systems 31(11): 1723-1733 (2012) |
| c6 | | Kuan-Hsien Ho, Xin-Wei Shih, Jie-Hong R. Jiang: Clock rescheduling for timing engineering change orders. ASP-DAC 2012: 517-522 |
| c5 | | Gwo-Ruey Yu, Kuan-Hsien Ho: Constraints on control input and output of polynomial fuzzy systems via a sum of squares approach. FUZZ-IEEE 2012: 1-6 |
| 2010 | ||
| j2 | | Kuan-Hsien Ho, Yen-Pin Chen, Jia-Wei Fang, Yao-Wen Chang: ECO Timing Optimization Using Spare Cells and Technology Remapping. IEEE Trans. on CAD of Integrated Circuits and Systems 29(5): 697-710 (2010) |
| c4 | | Kuan-Hsien Ho, Jie-Hong R. Jiang, Yao-Wen Chang: TRECO: dynamic technology remapping for timing engineering change orders. ASP-DAC 2010: 331-336 |
| c3 | | Xin-Wei Shih, Hsu-Chieh Lee, Kuan-Hsien Ho, Yao-Wen Chang: High variation-tolerant obstacle-avoiding clock mesh synthesis with symmetrical driving trees. ICCAD 2010: 452-457 |
| 2009 | ||
| j1 | | Po-Yuan Chen, Kuan-Hsien Ho, TingTing Hwang: Skew-aware polarity assignment in clock tree. ACM Trans. Design Autom. Electr. Syst. 14(2) (2009) |
| 2008 | ||
| c2 | | Jia-Wei Fang, Kuan-Hsien Ho, Yao-Wen Chang: Routing for chip-package-board co-design considering differential pairs. ICCAD 2008: 512-517 |
| 2007 | ||
| c1 | | Po-Yuan Chen, Kuan-Hsien Ho, TingTing Hwang: Skew aware polarity assignment in clock tree. ICCAD 2007: 376-379 |
| 1 | Yao-Wen Chang | |
| 2 | Po-Yuan Chen | |
| 3 | Yen-Pin Chen | |
| 4 | Jia-Wei Fang | |
| 5 | TingTing Hwang | |
| 6 | Jie-Hong Roland Jiang (Jie-Hong R. Jiang) | |
| 7 | Hsu-Chieh Lee | |
| 8 | Xin-Wei Shih | |
| 9 | Gwo-Ruey Yu |
Colors in the list of coauthors
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