Tsung-Yi Ho

Yan Luo, Krishnendu Chakrabarty, Tsung-Yi Ho: Error Recovery in Cyberphysical Digital Microfluidic Biochips. IEEE Trans. on CAD of Integrated Circuits and Systems 32(1): 59-72 (2013)

Jia-Wen Chang, Sheng-Han Yeh, Tsung-Wei Huang, Tsung-Yi Ho: Integrated Fluidic-Chip Co-Design Methodology for Digital Microfluidic Biochips. IEEE Trans. on CAD of Integrated Circuits and Systems 32(2): 216-227 (2013)

Po-Hsun Wu, Mark Po-Hung Lin, Tung-Chieh Chen, Tsung-Yi Ho, Yu-Chuan Chen, Shun-Ren Siao, Shu-Hung Lin: 1-D Cell Generation With Printability Enhancement. IEEE Trans. on CAD of Integrated Circuits and Systems 32(3): 419-432 (2013)

Trung Anh Dinh, Shigeru Yamashita, Tsung-Yi Ho, Yuko Hara-Azumi: A clique-based approach to find binding and scheduling result in flow-based microfluidic biochips. ASP-DAC 2013: 199-204

Wajid Hassan Minhass, Paul Pop, Jan Madsen, Tsung-Yi Ho: Control synthesis for the flow-based microfluidic large-scale integration biochips. ASP-DAC 2013: 205-212

Kai-Han Tseng, Sheng-Chi You, Wajid Hassan Minhass, Tsung-Yi Ho, Paul Pop: A network-flow based valve-switching aware binding algorithm for flow-based microfluidic biochips. ASP-DAC 2013: 213-218

Jiun-Li Lin, Po-Hsun Wu, Tsung-Yi Ho: A novel cell placement algorithm for flexible TFT circuit with mechanical strain and temperature consideration. ASP-DAC 2013: 491-496

Kai-Han Tseng, Sheng-Chi You, Jhe-Yu Liou, Tsung-Yi Ho: A top-down synthesis methodology for flow-based microfluidic biochips considering valve-switching minimization. ISPD 2013: 123-129

Po-Hsun Wu, Tsung-Yi Ho: Bus-driven floorplanning with bus pin assignment and deviation minimization. Integration 45(4): 405-426 (2012)

Kai-Ti Hsu, Subarna Sinha, Yu-Chuan Pi, Tsung-Yi Ho: A Hierarchy-Based Distributed Algorithm for Layout Geometry Operations. IEEE Trans. on CAD of Integrated Circuits and Systems 31(10): 1546-1557 (2012)

Yi-Ling Hsieh, Tsung-Yi Ho, Krishnendu Chakrabarty: A Reagent-Saving Mixing Algorithm for Preparing Multiple-Target Biochemical Samples Using Digital Microfluidics. IEEE Trans. on CAD of Integrated Circuits and Systems 31(11): 1656-1669 (2012)

Jing-Wei Lin, Tsung-Yi Ho, Iris Hui-Ru Jiang: Reliability-Driven Power/Ground Routing for Analog ICs. ACM Trans. Design Autom. Electr. Syst. 17(1): 6 (2012)

Kuan-Yu Lin, Hong-Ting Lin, Tsung-Yi Ho, Chia-Chun Tsai: Load-balanced clock tree synthesis with adjustable delay buffer insertion for clock skew reduction in multiple dynamic supply voltage designs. ACM Trans. Design Autom. Electr. Syst. 17(3): 34 (2012)

Jia-Wen Chang, Tsung-Wei Huang, Tsung-Yi Ho: An ILP-based obstacle-avoiding routing algorithm for pin-constrained EWOD chips. ASP-DAC 2012: 67-72

Yan Luo, Krishnendu Chakrabarty, Tsung-Yi Ho: A cyberphysical synthesis approach for error recovery in digital microfluidic biochips. DATE 2012: 1239-1244

Sheng-Han Yeh, Jia-Wen Chang, Tsung-Wei Huang, Tsung-Yi Ho: Voltage-aware chip-level design for reliability-driven pin-constrained EWOD chips. ICCAD 2012: 353-360

Yan Luo, Krishnendu Chakrabarty, Tsung-Yi Ho: Dictionary-based error recovery in cyberphysical digital-microfluidic biochips. ICCAD 2012: 369-376

Po-Hsun Wu, Mark Po-Hung Lin, Yang-Ru Chen, Bing-Shiun Chou, Tung-Chieh Chen, Tsung-Yi Ho, Bin-Da Liu: Performance-driven analog placement considering monotonic current paths. ICCAD 2012: 613-619

Yi-Ling Hsieh, Tsung-Yi Ho, Krishnendu Chakrabarty: Design methodology for sample preparation on digital microfluidic biochips. ICCD 2012: 189-194

Tsung-Wei Huang, Jia-Wen Chang, Tsung-Yi Ho: Integrated fluidic-chip co-design methodology for digital microfluidic biochips. ISPD 2012: 49-56

Tsung-Wei Huang, Tsung-Yi Ho: A Two-Stage Integer Linear Programming-Based Droplet Routing Algorithm for Pin-Constrained Digital Microfluidic Biochips. IEEE Trans. on CAD of Integrated Circuits and Systems 30(2): 215-228 (2011)

Sheng Chou, Cheng-Shen Han, Po-Kai Huang, Ko-Fan Tien, Tsung-Yi Ho: An Effective and Efficient Framework for Clock Latency Range Aware Clock Network Synthesis. IEEE Trans. on CAD of Integrated Circuits and Systems 30(7): 1045-1057 (2011)

Tsung-Wei Huang, Shih-Yuan Yeh, Tsung-Yi Ho: A Network-Flow Based Pin-Count Aware Routing Algorithm for Broadcast-Addressing EWOD Chips. IEEE Trans. on CAD of Integrated Circuits and Systems 30(12): 1786-1799 (2011)

Kuan-Yu Lin, Hong-Ting Lin, Tsung-Yi Ho: An efficient algorithm of adjustable delay buffer insertion for clock skew minimization in multiple dynamic supply voltage designs. ASP-DAC 2011: 825-830

Tsung-Yi Ho, Krishnendu Chakrabarty, Paul Pop: Digital microfluidic biochips: recent research and emerging challenges. CODES+ISSS 2011: 335-344

Krishnendu Chakrabarty, Paul Pop, Tsung-Yi Ho: Digital microfluidic biochips: functional diversity, more than moore, and cyberphysical systems. CODES+ISSS 2011: 377-378

Kai-Ti Hsu, Subarna Sinha, Yu-Chuan Pi, Charles Chiang, Tsung-Yi Ho: A distributed algorithm for layout geometry operations. DAC 2011: 182-187

Tsung-Wei Huang, Hong-Yan Su, Tsung-Yi Ho: Progressive network-flow based power-aware broadcast addressing for pin-constrained digital microfluidic biochips. DAC 2011: 741-746

Yi-Lin Chuang, Hong-Ting Lin, Tsung-Yi Ho, Yao-Wen Chang, Diana Marculescu: PRICE: Power reduction by placement and clock-network co-synthesis for pulsed-latch designs. ICCAD 2011: 85-90

Tsung-Wei Huang, Tsung-Yi Ho, Krishnendu Chakrabarty: Reliability-oriented broadcast electrode-addressing for pin-constrained digital microfluidic biochips. ICCAD 2011: 448-455

Hong-Ting Lin, Yi-Lin Chuang, Tsung-Yi Ho: Pulsed-latch-based clock tree migration for dynamic power reduction. ISLPED 2011: 39-44

Po-Hsun Wu, Tsung-Yi Ho: Thermal-aware bus-driven floorplanning. ISLPED 2011: 205-210

Ping-Hung Yuh, Cliff Chiung-Yu Lin, Tsung-Wei Huang, Tsung-Yi Ho, Chia-Lin Yang, Yao-Wen Chang: A SAT-based routing algorithm for cross-referencing biochips. SLIP 2011: 1-7

Tsung-Wei Huang, Yan-You Lin, Jia-Wen Chang, Tsung-Yi Ho: Recent research and emerging challenges in design and optimization for digital microfluidic biochips. SoCC 2011: 12-17

Yi-Ling Hsieh, Tsung-Yi Ho: Automated Physical Design of Microchip-Based Capillary Electrophoresis Systems. VLSI Design 2011: 165-170

Tsung-Wei Huang, Chun-Hsien Lin, Tsung-Yi Ho: A Contamination Aware Droplet Routing Algorithm for the Synthesis of Digital Microfluidic Biochips. IEEE Trans. on CAD of Integrated Circuits and Systems 29(11): 1682-1695 (2010)

Bo-Shiun Wu, Tsung-Yi Ho: Bus-pin-aware bus-driven floorplanning. ACM Great Lakes Symposium on VLSI 2010: 27-32

Tsung-Wei Huang, Shih-Yuan Yeh, Tsung-Yi Ho: A network-flow based pin-count aware routing algorithm for broadcast electrode-addressing EWOD chips. ICCAD 2010: 425-431

Tsung-Yi Ho, Jun Zeng, Krishnendu Chakrabarty: Digital microfluidic biochips: A vision for functional diversity and more than moore. ICCAD 2010: 578-585

Tsung-Wei Huang, Tsung-Yi Ho: A two-stage ILP-based droplet routing algorithm for pin-constrained digital microfluidic biochips. ISPD 2010: 201-208

Tsung-Yi Ho, Sheng-Hung Liu: Fast Legalization for Standard Cell Placement with Simultaneous Wirelength and Displacement Minimization. VLSI-SoC (Selected Papers) 2010: 291-311

Tsung-Yi Ho, Sheng-Hung Liu: Fast legalization for standard cell placement with simultaneous wirelength and displacement minimization. VLSI-SoC 2010: 369-374

Tsung-Yi Ho: PIXAR: A performance-driven X-architecture router based on a novel multilevel framework. Integration 42(3): 400-408 (2009)

Tsung-Wei Huang, Chun-Hsien Lin, Tsung-Yi Ho: A contamination aware droplet routing algorithm for digital microfluidic biochips. ICCAD 2009: 151-156

Tsung-Wei Huang, Tsung-Yi Ho: A fast routability- and performance-driven droplet routing algorithm for digital microfluidic biochips. ICCD 2009: 445-450

Sheng Chou, Tsung-Yi Ho: OAL: An obstacle-aware legalization in standard cell placement with displacement minimization. SoCC 2009: 329-332

Tsung-Yi Ho: A Performance-Driven Multilevel Framework for the X-Based Full-Chip Router. PATMOS 2008: 209-218

Tsung-Yi Ho, Yao-Wen Chang, Sao-Jie Chen: Multilevel routing with jumper insertion for antenna avoidance. Integration 39(4): 420-432 (2006)

Tsung-Yi Ho, Yao-Wen Chang, Sao-Jie Chen, D. T. Lee: Crosstalk- and performance-driven multilevel full-chip routing. IEEE Trans. on CAD of Integrated Circuits and Systems 24(6): 869-878 (2005)

Tsung-Yi Ho, Chen-Feng Chang, Yao-Wen Chang, Sao-Jie Chen: Multilevel full-chip routing for the X-based architecture. DAC 2005: 597-602

Tsung-Yi Ho, Yao-Wen Chang, Sao-Jie Chen: Multilevel routing with antenna avoidance. ISPD 2004: 34-40

Tsung-Yi Ho, Yao-Wen Chang, Sao-Jie Chen: Multilevel routing with jumper insertion for antenna avoidance. SoCC 2004: 63-66

Tsung-Yi Ho, Yao-Wen Chang, Sao-Jie Chen, D. T. Lee: A Fast Crosstalk- and Performance-Driven Multilevel Routing System. ICCAD 2003: 382-387