Please note: This is a beta version of the new dblp website.
You can find the classic dblp view of this page here.
You can find the classic dblp view of this page here.
Raymond R. Hoare
Raymond Hoare
2000 – 2009
- 2008
[j10]Raymond R. Hoare, Zhu Ding, Alex K. Jones: A two-stage hardware scheduler combining greedy and optimal scheduling. J. Parallel Distrib. Comput. 68(11): 1437-1451 (2008)- [j9]Alex K. Jones, Swapna R. Dontharaju, Shen Chih Tung, Leonid Mats, Peter J. Hawrylak, Raymond R. Hoare, James T. Cain, Marlin H. Mickle: Radio frequency identification prototyping. ACM Trans. Design Autom. Electr. Syst. 13(2) (2008)
- [c26]Ying Yu, Raymond R. Hoare, Alex K. Jones: A CAM-based intrusion detection system for single-packet attack detection. IPDPS 2008: 1-8
- 2007
- [j8]Alex K. Jones, Raymond Hoare, Swapna R. Dontharaju, Shen Chih Tung, Ralph Sprang, Joshua Fazekas, James T. Cain, Marlin H. Mickle: An automated, FPGA-based reconfigurable, low-power RFID tag. Microprocessors and Microsystems 31(2): 116-134 (2007)
- [c25]Alex K. Jones, Raymond R. Hoare, Joseph St. Onge, Joshua M. Lucas, Shuyi Shao, Rami G. Melhem: Linking Compilation and Visualization for Massively Parallel Programs. IPDPS 2007: 1-8
- 2006
- [j7]Raymond R. Hoare, Alex K. Jones, Dara Kusic, Joshua Fazekas, John Foster, Shen Chih Tung, Michael L. McCloud: Rapid VLIW Processor Customization for Signal Processing Applications Using Combinational Hardware Functions. EURASIP J. Adv. Sig. Proc. 2006 (2006)
- [j6]Jeffrey William Schuster, Kshitij Gupta, Raymond Hoare, Alex K. Jones: Speech Silicon: An FPGA Architecture for Real-Time Hidden Markov-Model-Based Speech Recognition. EURASIP J. Emb. Sys. 2006 (2006)
- [j5]Alex K. Jones, Swapna R. Dontharaju, Shen Chih Tung, Peter J. Hawrylak, Leonid Mats, Raymond R. Hoare, James T. Cain, Marlin H. Mickle: Passive active radio frequency identification tags. IJRFITA 1(1): 52-73 (2006)
- [j4]Gayatri Mehta, Justin Stander, Joshua M. Lucas, Raymond R. Hoare, Brady Hunsaker, Alex K. Jones: A Low-Energy Reconfigurable Fabric for the SuperCISC Architecture. J. Low Power Electronics 2(2): 148-164 (2006)
- [j3]Joshua M. Lucas, Raymond Hoare, Ivan S. Kourtev, Alex K. Jones: Technology mapping for Field Programmable Gate Arrays using Content-Addressable Memory (CAM). Microprocessors and Microsystems 30(7): 445-456 (2006)
- [j2]Alex K. Jones, Raymond Hoare, Dara Kusic, Gayatri Mehta, Joshua Fazekas, John Foster: Reducing power while increasing performance with supercisc. ACM Trans. Embedded Comput. Syst. 5(3): 658-686 (2006)
- [c24]Alex K. Jones, Raymond R. Hoare, Swapna R. Dontharaju, Shen Chih Tung, Ralph Sprang, Joshua Fazekas, James T. Cain, Marlin H. Mickle: An automated, reconfigurable, low-power RFID tag. DAC 2006: 131-136
- [c23]Alex K. Jones, Raymond R. Hoare, Swapna R. Dontharaju, Shen Chih Tung, Ralph Sprang, Joshua Fazekas, James T. Cain, Marlin H. Mickle: A Field Programmable RFID Tag and Associated Design Flow. FCCM 2006: 165-174
- [c22]Raymond R. Hoare, Ivan S. Kourtev, Alex K. Jones: Technology Mapping for Field Programmable Gate Arrays using Content-Addressable Memory (CAM). FCCM 2006: 299-300
- [c21]Gayatri Mehta, Raymond R. Hoare, Justin Stander, Alex K. Jones: A Low-Energy Reconfigurable Fabric for the SuperCISC Architecture. FCCM 2006: 309-310
- [c20]Gayatri Mehta, Raymond R. Hoare, Justin Stander, Alex K. Jones: Design space exploration for low-power reconfigurable fabrics. IPDPS 2006
- [c19]Jeffrey William Schuster, Kshitij Gupta, Raymond R. Hoare: Speech silicon AM: an FPGA-based acoustic modeling pipeline for hidden Markov model based speech recognition. IPDPS 2006
- [c18]Ying Yu, Raymond R. Hoare, Alex K. Jones, Ralph Sprang: A hybrid encoding scheme for efficient single-cycle range matching in content addressable memory. ISCAS 2006
- [c17]Raymond R. Hoare, Zhu Ding, Alex K. Jones: Interconnect routing and scheduling - A near-optimal real-time hardware scheduler for large cardinality crossbar switches. SC 2006: 94
- [c16]Zhu Ding, Raymond R. Hoare, Alex K. Jones, Rami G. Melhem: Interconnect routing and scheduling - Level-wise scheduling algorithm for fat tree interconnection networks. SC 2006: 96
- 2005
- [j1]Raymond R. Hoare, Zhu Ding, Shen Chih Tung, Rami G. Melhem, Alex K. Jones: A framework for the design, synthesis and cycle-accurate simulation of multiprocessor networks. J. Parallel Distrib. Comput. 65(10): 1237-1252 (2005)
- [c15]Joshua M. Lucas, Raymond Hoare, Alex K. Jones: Optimizing Technology Mapping for FPGAs Using CAMs. FCCM 2005: 293-294
- [c14]Alex K. Jones, Raymond Hoare, Dara Kusic, Joshua Fazekas, John Foster: An FPGA-based VLIW processor with custom hardware execution. FPGA 2005: 107-117
- [c13]Zhu Ding, Raymond R. Hoare, Alex K. Jones, Dan Li, Shou-Kuo Shao, Shen-Chien Tung, Jiang Zheng, Rami G. Melhem: Switch Design to Enable Predictive Multiplexed Switching in Multiprocessor Networks. IPDPS 2005
- [c12]Dara Kusic, Raymond Hoare, Alex K. Jones, Joshua Fazekas, John Foster: Extracting Speedup From C-Code With Poor Instruction-Level Parallelism. IPDPS 2005
- [c11]Kevin J. Barker, Alan F. Benner, Raymond R. Hoare, Adolfy Hoisie, Alex K. Jones, Darren J. Kerbyson, Dan Li, Rami G. Melhem, Ramakrishnan Rajamony, Eugen Schenfeld, Shuyi Shao, Craig B. Stunkel, Peter Walker: On the Feasibility of Optical Circuit Switching for High Performance Computing Systems. SC 2005: 16
- 2004
- [c10]Raymond Hoare, Shen Chih Tung, Katrina Werger: An 88-Way Multiprocessor within an FPGA with Customizable Instructions. IPDPS 2004
- 2003
- [c9]Ivan S. Kourtev, Raymond R. Hoare, Steven P. Levitan, Tom Cain, Bruce R. Childers, Donald M. Chiarulli, David L. Landis: Short Courses in System-on-a-Chip (SoC) Design. MSE 2003: 126-127
- [c8]Raymond Hoare, Shen Chih Tung: Combining Mentor Graphics? HDL Designer FPGA Flow with a Reconfigurable System on a Programmable Chip, Educational Opportunity or Insanity? MSE 2003: 128-130
- 2002
- [c7]
- [c6]Raymond R. Hoare, D. Swope, S. Bailey: A Width Expansion of MMX/SIMD Processing Architecture on an FPGA. IASTED PDCS 2002: 562-566
- 2001
- [c5]T. A. Johnson, Raymond R. Hoare: Cyclical Cascade Chains: A Dynamic Barrier Synchronization Mechanism for Multiprocessor Systems. IPDPS 2001: 193
- 2000
- [c4]
1990 – 1999
- 1998
- [c3]
- 1997
- [c2]Soohong P. Kim, Raymond Hoare, Henry G. Dietz: VLIW Across Multiple Superscalar Processors on a Single Chip. IEEE PACT 1997: 166-
- 1996
- [c1]Henry G. Dietz, Raymond Hoare, Timothy Mattox: A Fine-Grain Parallel Architecture Based on Barrier Synchronization. ICPP, Vol. 1 1996: 247-250
Coauthor Index
data released under the ODC-BY 1.0 license. See also our legal information page
last updated on 2012-12-02 21:00 CET by the dblp team