H. Peter Hofstee

H. Peter Hofstee: Cell Broadband Engine Processor. Encyclopedia of Parallel Computing 2011: 234-241

Peter Hofstee: The Next 25 Years of Computer Architecture? Euro-Par Workshops 2009: 7

Martti Forsell, Peter Hofstee, Ahmed Jerraya, Chris R. Jesshope, Uzi Vishkin, Jesper Larsson Träff: HPPC 2009 Panel: Are Many-Core Computer Vendors on Track? Euro-Par Workshops 2009: 9-15

Bernard Frischer, Dean Abernathy, Gabriele Guidi, Joel Myers, Cassie Thibodeau, Antonio Salvemini, Pascal Müller, Peter Hofstee, Barry Minor: Rome Reborn. SIGGRAPH New Tech Demos 2008: 34

H. Peter Hofstee, Ashwini K. Nanda, John J. Ritsko: Preface. IBM Journal of Research and Development 51(5): 501-502 (2007)

Kanna Shimizu, H. Peter Hofstee, John S. Liberty: Cell Broadband Engine processor vault security architecture. IBM Journal of Research and Development 51(5): 521-528 (2007)

Brian K. Flachs, Shigehiro Asano, Sang H. Dhong, H. Peter Hofstee, Gilles Gervais, Roy Kim, Tien Le, Peichun Liu, Jens Leenstra, John S. Liberty, Brad W. Michael, Hwa-Joon Oh, Silvia M. Müller, Osamu Takahashi, Koji Hirairi, Atsushi Kawasumi, Hiroaki Murakami, Hiromi Noro, Shoji Onishi, Juergen Pille, Joel Silberman, Suksoon Yong, Akiyuki Hatakeyama, Yukio Watanabe, Naoka Yano, Daniel A. Brokenshire, Mohammad Peyravian, VanDung To, Eiji Iwata: Microarchitecture and implementation of the synergistic processor in 65-nm and 90-nm SOI. IBM Journal of Research and Development 51(5): 529-544 (2007)

Michael T. Clark, Peter Hofstee, Edward J. Barragy, Ian Buck, Stephen W. Keckler: The future of multi-core technologies. CLUSTER 2007

Michael Gschwind, H. Peter Hofstee, Brian K. Flachs, Martin Hopkins, Yukio Watanabe, Takeshi Yamazaki: Synergistic Processing in Cell's Multicore Architecture. IEEE Micro 26(2): 10-24 (2006)

Dac Pham, Hans-Werner Anderson, Erwin Behnen, Mark Bolliger, Sanjay Gupta, H. Peter Hofstee, Paul E. Harvey, Charles R. Johns, James A. Kahle, Atsushi Kameyama, John M. Keaty, Bob Le, Sang Lee, Tuyen V. Nguyen, John G. Petrovick, Mydung Pham, Juergen Pille, Stephen D. Posluszny, Mack W. Riley, Joseph Verock, James D. Warnock, Steve Weitzel, Dieter F. Wendel: Key features of the design methodology enabling a multi-core SoC implementation of a first-generation CELL processor. ASP-DAC 2006: 871-878

H. Peter Hofstee: Invited speakers II - Real-time supercomputing and technology for games and entertainment. SC 2006: 199

James A. Kahle, Michael N. Day, H. Peter Hofstee, Charles R. Johns, Theodore R. Maeurer, David J. Shippy: Introduction to the Cell multiprocessor. IBM Journal of Research and Development 49(4-5): 589-604 (2005)

H. Peter Hofstee, Michael N. Day: Hardware and software architectures for the CELL processor. CODES+ISSS 2005: 1

H. Peter Hofstee: Power Efficient Processor Architecture and The Cell Processor. HPCA 2005: 258-262

H. Peter Hofstee: Communication and Synchronization in the Cell Processor - Invited Talk. CPA 2005: 397

H. Peter Hofstee: Power-Constrained Microprocessor Design. ICCD 2002: 14-16

H. Peter Hofstee, Jun Sawada: Derivation of a rotator circuit with homogeneous interconnect. Inf. Process. Lett. 77(2-4): 131-135 (2001)

Wendy Belluomini, Chris J. Myers, H. Peter Hofstee: Timed circuit verification using TEL structures. IEEE Trans. on CAD of Integrated Circuits and Systems 20(1): 129-146 (2001)

David H. Allen, Sang H. Dhong, H. Peter Hofstee, Jens Leenstra, Kevin J. Nowka, Daniel L. Stasiak, Dieter F. Wendel: Custom circuit design as a driver of microprocessor performance. IBM Journal of Research and Development 44(6): 799-822 (2000)

Stephen D. Posluszny, N. Aoki, David Boerstler, P. Coulman, Sang H. Dhong, Brian K. Flachs, H. Peter Hofstee, N. Kojima, Ohsang Kwon, K. Lee, D. Meltzer, Kevin J. Nowka, J. Park, J. Peter, Joel Silberman, Osamu Takahashi, Paul Villarrubia: "Timing closure by design, " a high frequency microprocessor design methodology. DAC 2000: 712-717

Wendy Belluomini, Chris J. Myers, H. Peter Hofstee: Verification of Delayed-Reset Domino Circuits Using ATACS. ASYNC 1999: 3-12

Osamu Takahashi, Joel Silberman, Sang H. Dhong, H. Peter Hofstee, N. Aoki: A 690 ps read-access latency register file for a GHz integer microprocessor. ICCD 1998: 6-10

Stephen D. Posluszny, N. Aoki, David Boerstler, Jeffrey L. Burns, Sang H. Dhong, Uttam Ghoshal, H. Peter Hofstee, David P. LaPotin, K. Lee, D. Meltzer, Hung C. Ngo, Kevin J. Nowka, Joel Silberman, Osamu Takahashi, Ivan Vo: Design methodology for a 1.0 GHz microprocessor. ICCD 1998: 17-23

David F. Heidel, Sang H. Dhong, H. Peter Hofstee, Michael Immediato, Kevin J. Nowka, Joel Silberman, Kevin G. Stawiasz: High-Speed Serializing/De-Serializing Design-For-Test Method for Evaluating a 1 GHz Microprocessor. VTS 1998: 234-238

Kevin J. Nowka, H. Peter Hofstee: Circuits and Microarchitecture for Gigahertz VLSI Designs. ARVLSI 1997: 284-287

H. Peter Hofstee: Distributing a Class of Sequential Programs. Sci. Comput. Program. 22(1-2): 45-65 (1994)

H. Peter Hofstee: Distributing a Class of Sequential Programs. MPC 1992: 139-162

H. Peter Hofstee, Johan J. Lukkien, Jan L. A. van de Snepscheut: A Distributed Implementation of a Task Pool. Research Directions in High-Level Parallel Programming Languages 1991: 338-348

H. Peter Hofstee, Alain J. Martin, Jan L. A. van de Snepscheut: Distributed Sorting. Sci. Comput. Program. 15(2-3): 119-133 (1990)