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 | 2012 | |
|---|---|---|
| j12 |      | Kentaro Tomii, Yoshito Sawada, Shinya Honda: Convergent evolution in structural elements of proteins investigated using cross profile analysis. BMC Bioinformatics 13: 11 (2012) |
| j11 | | Krzysztof Jozwik, Hiroyuki Tomiyama, Masato Edahiro, Shinya Honda, Hiroaki Takada: Comparison of Preemption Schemes for Partially Reconfigurable FPGAs. Embedded Systems Letters 4(2): 45-48 (2012) |
| j10 | | Krzysztof Jozwik, Hiroyuki Tomiyama, Shinya Honda, Hiroaki Takada: A Novel Framework for Effective Preemptive Hardware Multitasking on FPGAs. IEICE Transactions 95-D(2): 345-353 (2012) |
| c17 | | Yuko Hara-Azumi, Toshinobu Matsuba, Hiroyuki Tomiyama, Shinya Honda, Hiroaki Takada: Selective Resource Sharing with RT-Level Retiming for Clock Enhancement in High-Level Synthesis. HPCC-ICESS 2012: 1534-1540 |
| c16 | | Yutaka Matsubara, Yasumasa Sano, Shinya Honda, Hiroaki Takada: An Open-Source Flexible Scheduling Simulator for Real-Time Applications. ISORC 2012: 16-22 |
| c15 | | Daniel Sangorrín, Shinya Honda, Hiroaki Takada: Reliable Device Sharing Mechanisms for Dual-OS Embedded Trusted Computing. TRUST 2012: 74-91 |
| 2011 | ||
| c14 | | Krzysztof Jozwik, Hiroyuki Tomiyama, Masato Edahiro, Shinya Honda, Hiroaki Takada: Rainbow: An OS Extension for Hardware Multitasking on Dynamically Partially Reconfigurable FPGAs. ReConFig 2011: 416-421 |
| 2010 | ||
| j9 | | Yuko Hara, Hiroyuki Tomiyama, Shinya Honda, Hiroaki Takada: Partitioning of Behavioral Descriptions with Exploiting Function-Level Parallelism. IEICE Transactions 93-A(2): 488-499 (2010) |
| j8 | | Yuki Ando, Seiya Shibata, Shinya Honda, Hiroyuki Tomiyama, Hiroaki Takada: Automatic Communication Synthesis with Hardware Sharing for Multi-Processor SoC Design. IEICE Transactions 93-A(12): 2509-2516 (2010) |
| c13 | | Toshinobu Matsuba, Yuko Hara, Hiroyuki Tomiyama, Shinya Honda, Hiroaki Takada: Aggressive Register Unsharing Based on SSA Transformation for Clock Enhancement in High-Level Synthesis. DELTA 2010: 87-92 |
| c12 | | Krzysztof Jozwik, Hiroyuki Tomiyama, Shinya Honda, Hiroaki Takada: A Novel Mechanism for Effective Hardware Task Preemption in Dynamically Reconfigurable Systems. FPL 2010: 352-355 |
| c11 | | Yuki Ando, Seiya Shibata, Shinya Honda, Hiroyuki Tomiyama, Hiroaki Takada: Automatic communication synthesis with hardware sharing for design space exploration. ISCAS 2010: 1863-1866 |
| 2009 | ||
| j7 | | Yoshito Sawada, Shinya Honda: ProSeg: a database of local structures of protein segments. Journal of Computer-Aided Molecular Design 23(3): 163-169 (2009) |
| j6 | | Yuko Hara, Hiroyuki Tomiyama, Shinya Honda, Hiroaki Takada: Proposal and Quantitative Analysis of the CHStone Benchmark Program Suite for Practical C-based High-level Synthesis. JIP 17: 242-254 (2009) |
| 2008 | ||
| c10 | | Yuko Hara, Hiroyuki Tomiyama, Shinya Honda, Hiroaki Takada, Katsuya Ishii: CHStone: A benchmark program suite for practical C-based high-level synthesis. ISCAS 2008: 1192-1195 |
| 2007 | ||
| j5 | | Yuko Hara, Hiroyuki Tomiyama, Shinya Honda, Hiroaki Takada: Function Call Optimization for Efficient Behavioral Synthesis. IEICE Transactions 90-A(9): 2032-2036 (2007) |
| j4 | | Yuko Hara, Hiroyuki Tomiyama, Shinya Honda, Hiroaki Takada, Katsuya Ishii: Function-Level Partitioning of Sequential Programs for Efficient Behavioral Synthesis. IEICE Transactions 90-A(12): 2853-2862 (2007) |
| j3 | | Masaki Yamamoto, Shinya Honda, Hiroaki Takada, Kiyoshi Agusa, Hiroyuki Tomiyama, Kenji Mase, Nobuo Kawaguchi, Nobuyuki Kaneko: Practice and analysis of an extension course for training trainers of embedded software. SIGBED Review 4(1): 73-81 (2007) |
| c9 | | Shinya Honda, Hiroyuki Tomiyama, Hiroaki Takada: RTOS and Codesign Toolkit for Multiprocessor Systems-on-Chip. ASP-DAC 2007: 336-341 |
| c8 | | Yuko Hara, Hiroyuki Tomiyama, Shinya Honda, Hiroaki Takada, Katsuya Ishii: Complexity-constrainted partitioning of sequential programs for efficient behavioral synthesis. ACM Great Lakes Symposium on VLSI 2007: 365-370 |
| c7 | | Yuko Hara, Hiroyuki Tomiyama, Shinya Honda, Hiroaki Takada, Katsuya Ishii: Behavioral Synthesis of Double-Precision Floating-Point Adders with Function-Level Transformations: A Case Study. ICESS 2007: 261-270 |
| c6 | | Takashi Furukawa, Shinya Honda, Hiroyuki Tomiyama, Hiroaki Takada: A Hardware/Software Cosimulator with RTOS Supports for Multiprocessor Embedded Systems. ICESS 2007: 283-294 |
| 2006 | ||
| c5 | | Yuko Hara, Hiroyuki Tomiyama, Shinya Honda, Hiroaki Takada: Function Call Optimization in Behavioral Synthesis. DSD 2006: 522-529 |
| 2005 | ||
| j2 | | Hiroyuki Tomiyama, Shin-ichiro Chikada, Shinya Honda, Hiroaki Takada: An RTOS-Based Design and Validation Methodology for Embedded Systems. IEICE Transactions 88-D(9): 2205-2208 (2005) |
| j1 | | Masaki Yamamoto, Hiroyuki Tomiyama, Hiroaki Takada, Kiyoshi Agusa, Kenji Mase, Nobuo Kawaguchi, Shinya Honda, Nobuyuki Kaneko: NEXCESS: Nagoya university extension courses for embedded software specialists. SIGBED Review 2(4): 20-24 (2005) |
| c4 | | Shin-ichiro Chikada, Shinya Honda, Hiroyuki Tomiyama, Hiroaki Takada: Cosimulation of ITRON-based embedded software with SystemC. HLDVT 2005: 71-76 |
| 2004 | ||
| c3 | | Shinya Honda, Takayuki Wakabayashi, Hiroyuki Tomiyama, Hiroaki Takada: RTOS-centric hardware/software cosimulator for embedded system design. CODES+ISSS 2004: 158-163 |
| 2003 | ||
| c2 | | Shinya Honda, Hiroaki Takada: Evaluation of Applying SpecC to the Integrated Design Method of Device Driver and Device. DATE 2003: 20138-20143 |
| c1 | | Hiroaki Takada, Shinya Honda, Reiji Nishiyama, Hiroshi Yuyama: Hardware/Software Co-Configuration for Multiprocessor SoPC. WSTFEUS 2003: 7-8 |
Colors in the list of coauthors
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