Takahiro Hozumi

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	2000
c6		Takahiro Hozumi, Osamu Kakusho, Kazuharu Yamato: An Evolutionary Computing Approach to Multilevel Logic Synthesis Using Various Logic Operations. ISMVL 2000: 259-264
	1999
c5		Takahiro Hozumi, Osamu Kakusho, Yutaka Hata: The Output Permutation for the Multiple-Valued Logic Minimization with Universal Literals. ISMVL 1999: 105-109
	1998
c4		Takahiro Hozumi, Osamu Kakusho, Yutaka Hata: On Low Cost Realization of Multiple-Valued Logic Functions. ISMVL 1998: 233-238
	1997
c3		Yutaka Hata, Kiyoshi Hayase, Takahiro Hozumi, Naotake Kamiura, Kazuharu Yamato: Multiple-Valued Logic Minimization by Genetic Algorithms. ISMVL 1997: 97-102
	1995
c2		Takahiro Hozumi, Naotake Kamiura, Yutaka Hata, Kazuharu Yamato: Multiple-Valued Logic Design Using Multiple-Valued EXOR. ISMVL 1995: 290-295
	1993
c1		Yutaka Hata, Takahiro Hozumi, Kazuharu Yamato: Gate Model Networks for Minimization of Multiple-Valued Logic Functions. ISMVL 1993: 29-34

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