- CSB - MetaPress - Google - Bing - Yahoo
 | 2012 | |
|---|---|---|
| c15 |      | Chin-Hung Su, Mohd Helmy Abd Wahab, Tsai-Ming Hsieh: Image Retrieval based on color and texture features. FSKD 2012: 1816-1819 |
| 2011 | ||
| j2 | | Hsin-Hsiung Huang, Jui-Hung Hung, Cheng-Chiang Lin, Tsai-Ming Hsieh: Wire Planning for Electromigration and Interference Avoidance in Analog Circuits. IEICE Transactions 94-A(11): 2402-2411 (2011) |
| c14 | | Jui-Hung Hung, Yao-Kai Yeh, Yung-Sheng Tseng, Tsai-Ming Hsieh: A new ECO technology for functional changes and removing timing violations. ISQED 2011: 634-638 |
| 2010 | ||
| j1 | | Hsi-An Chien, Cheng-Chiang Lin, Hsin-Hsiung Huang, Tsai-Ming Hsieh: Optimal Supply Voltage Assignment under Timing, Power and Area Constraints. IEICE Transactions 93-A(4): 761-768 (2010) |
| c13 | | Jui-Hung Hung, Yao-Kai Yeh, Yung-Sheng Tseng, Tsai-Ming Hsieh: Technology remapping for engineering change with wirelength consideration. ISCAS 2010: 2602-2605 |
| 2008 | ||
| c12 | | Hsin-Hsiung Huang, Hui-Yu Huang, Yu-Cheng Lin, Tsai-Ming Hsieh: Timing-driven obstacles-avoiding routing tree construction for a multiple-layer system. ISCAS 2008: 1200-1203 |
| c11 | | Hsin-Hsiung Huang, Shu-Ping Chang, Yu-Cheng Lin, Tsai-Ming Hsieh: Timing-driven X-architecture router among rectangular obstacles. ISCAS 2008: 1804-1807 |
| 2006 | ||
| c10 | | Hsin-Hsiung Huang, Yung-Ching Chen, Tsai-Ming Hsieh: A congestion-driven buffer planner with space reservation. ISCAS 2006 |
| 2005 | ||
| c9 | | Chin-Hui Wang, Yung-Ching Chen, Tsai-Ming Hsieh, Chih-Hung Lee, Hsin-Hsiung Huang: A new congestion and crosstalk aware router. ISCAS (6) 2005: 6234-6237 |
| c8 | | Chih-Hung Lee, Chin-Hung Su, Shih-Hsu Huang, Chih-Yuan Lin, Tsai-Ming Hsieh: Floorplanning with clock tree estimation. ISCAS (6) 2005: 6244-6247 |
| 2004 | ||
| c7 | | Yi-Lin Hsieh, Tsai-Ming Hsieh: A New Effective Congestion Model in Floorplan Design. DATE 2004: 1204-1209 |
| 2002 | ||
| c6 | | Chih-Hung Lee, Wen-Yu Fu, Chung-Chiao Chang, Tsai-Ming Hsieh: An efficient hierarchical approach for general floorplan area minimization. APCCAS (2) 2002: 347-352 |
| c5 | | Chih-Hung Lee, Yu-Chung Lin, Wen-Yu Fu, Chung-Chiao Chang, Tsai-Ming Hsieh: A New Formulation for SOC Floorplan Area Minimization Problem. DATE 2002: 1100 |
| c4 | | Chih-Hung Lee, Yi-Lin Hsieh, Hui-Chun Lee, Tsai-Ming Hsieh: Sequence-pair based placement with boundary constraints. ISCAS (1) 2002: 341-344 |
| c3 | | Chih-Hung Lee, Yu-Chung Lin, Hsin-Hsiung Huang, Tsai-Ming Hsieh: Structural Decomposition with Functional Considerations for Low Power. ISQED 2002: 464-469 |
| 2001 | ||
| c2 | | Po-Xun Chiu, Yu-Chung Lin, Yi-Ling Hsieh, Tsai-Ming Hsieh: Low power driven re-synthesis algorithm for heterogeneous FPGA under delay constraint. ISCAS (5) 2001: 519-522 |
| 2000 | ||
| c1 | | Yu-Chung Lin, Su-Feng Tseng, Tsai-Ming Hsieh: Cost minimization of partitioned circuits with complex resource constraints in FPGAs (poster abstract). FPGA 2000: 217 |
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