Wan-Ling Hsu

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	2012
j2		Juinn-Dar Huang, Chia-I Chen, Wan-Ling Hsu, Yen-Ting Lin, Jing-Yang Jou: Performance-Driven Architectural Synthesis for Distributed Register-File Microarchitecture with Inter-Island Delay. IEICE Transactions 95-A(2): 559-566 (2012)
	2011
j1		Juinn-Dar Huang, Chia-I Chen, Yen-Ting Lin, Wan-Ling Hsu: Communication Synthesis for Interconnect Minimization Targeting Distributed Register-File Microarchitecture. IEICE Transactions 94-A(4): 1151-1155 (2011)

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