Yarsun Hsu

Wei-Yu Tsai, Ching-Te Chiu, Jen-Ming Wu, Shawn S. H. Hsu, Yarsun Hsu: A Novel Low Gate-Count Pipeline Topology With Multiplexer-Flip-Flops for Serial Link. IEEE Trans. on Circuits and Systems 59-I(11): 2600-2610 (2012)

Ching-Te Chiu, Yu-Hao Hsu, Jen-Ming Wu, Shuo-Hung Hsu, Min-Sheng Kao, Hou-Cheng Tzeng, Ming-Chang Du, Ping-Ling Yang, Ming-Hao Lu, Fanta Chen, Hung-Yu Lin, Yarsun Hsu: An 8 × 8 20 Gbps Reconfigurable Load Balanced TDM Switch IC for High-Speed Networking. Signal Processing Systems 66(1): 57-73 (2012)

Shan-Jung Miao, Yin Men, Yarsun Hsu: Achieving Global Fairness for On-Chip Network Using Group Allocation. IPDPS Workshops 2012: 930-937

Wei-Yu Tsai, Ching-Te Chiu, Jen-Ming Wu, Shawn S. H. Hsu, Yarsun Hsu, Ying-Fang Tsao: A novel low gate-count serializer topology with Multiplexer-Flip-Flops. ISCAS 2012: 245-248

Yu-Hao Hsu, Yang-Syu Lin, Ching-Te Chiu, Jen-Ming Wu, Shuo-Hung Hsu, Fanta Chen, Min-Sheng Kao, Wei-Chih Lai, Yarsun Hsu: A 32Gbps low propagation delay 4×4 switch IC for feedback-based system in 0.13μm CMOS technology. ASP-DAC 2011: 105-106

Li-Wei Wu, Wei-Xiang Tang, Yarsun Hsu: A Novel Architecture and Routing Algorithm for Dynamic Reconfigurable Network-on-Chip. ISPA 2011: 177-182

Shan-Jung Miao, Yarsun Hsu: Group allocation: A novel fairness mechanism for on-chip network. NESEA 2011: 1-7

Hung-Jen Sun, Yarsun Hsu: Implementation and analysis of speculative flow control for on-chip interconnection network. NESEA 2011: 1-6

Tzer-Ta Tseng, Yarsun Hsu: A Flexible and Cost-Effective File-Wise Reliability Scheme for Storage Systems. HPCC 2010: 427-433

Yi-Chiun Fang, Chien-Kai Tseng, Yarsun Hsu: Emulation of Object-Based Storage Devices by a Virtual Machine. ICA3PP (2) 2010: 166-177

Yu-Hao Hsu, Yang-Syu Lin, Ching-Te Chiu, Jen-Ming Wu, Shuo-Hung Hsu, Fanta Chen, Min-Sheng Kao, Yarsun Hsu: A 32Gbps low propagation delay 4×4 switch IC for feedback-based system in 0.13μm CMOS technology. ISCAS 2010: 581-584

Wei-Yu Tsai, Ching-Te Chiu, Jen-Ming Wu, Shuo-Hung Hsu, Yarsun Hsu: A novel MUX-FF circuit for low power and high speed serial link interfaces. ISCAS 2010: 4305-4308

Chi-Fu Chang, Yarsun Hsu: A System Exploration Platform for Network-on-Chip. ISPA 2010: 359-366

Jwo-An Lin, Yung-Chou Tsai, Tay-Jyi Lin, Yarsun Hsu: Cycle Stealing and Channel Management for On-Chip Networks. HPCC 2008: 53-60

Yu-Hao Hsu, Ming-Hao Lu, Ping-Ling Yang, Fanta Chen, You-Hung Li, Min-Sheng Kao, Chih-Hsing Lin, Ching-Te Chiu, Jen-Ming Wu, Shuo-Hung Hsu, Yarsun Hsu: A 28Gbps 4×4 switch with low jitter SerDes using area-saving RF model in 0.13µm CMOS technology. ISCAS 2008: 3086-3089

Sheng-Kai Hung, Yarsun Hsu: Reliable Parallel File System with Parity Cache Table Support. IEICE Transactions 90-D(1): 22-29 (2007)

Lungpin Yeh, Juei-Ting Sun, Sheng-Kai Hung, Yarsun Hsu: A Windows-Based Parallel File System. HPCC 2007: 7-18

Po-Chun Liu, Sheng-Kai Hung, Yarsun Hsu: Security Enhancement and Performance Evaluation of an Object-Based Storage System. HPCC 2007: 408-419

Ching-Te Chiu, Yu-Hao Hsu, Min-Sheng Kao, Hou-Cheng Tzeng, Ming-Chang Du, Ping-Ling Yang, Ming-Hao Lu, Fanta Chen, Hung-Yu Lin, Jen-Ming Wu, Shuo-Hung Hsu, Yarsun Hsu: A Scalable Load Balanced Birkhoff-von Neumann Symmetric TDM Switch IC for High-Speed Networking Applications. ISCAS 2007: 2754-2757

Hsiang-Ju Hsu, Ching-Te Chiu, Yarsun Hsu: Design of ultra low power CML MUXs and latches with forward body bias. SoCC 2007: 141-144

Sheng-Kai Hung, Yarsun Hsu: Striping Cache: A Global Cache for Striped Network File System. Asia-Pacific Computer Systems Architecture Conference 2006: 387-393

Sheng-Kai Hung, Yarsun Hsu: DPCT: Distributed Parity Cache Table for Redundant Parallel File System. HPCC 2006: 320-329

Sheng-Kai Hung, Yarsun Hsu: Modularized Redundant Parallel Virtual File System. Asia-Pacific Computer Systems Architecture Conference 2005: 186-199

Ching-Te Chiu, Jen-Ming Wu, Shuo-Hung Hsu, Min-Sheng Kao, Chih-Hsien Jen, Yarsun Hsu: A 10 Gb/s Wide-Band Current-Mode Logic I/O Interface for High-Speed Interconnect in 0.18μm CMOS Technology. SoCC 2005: 257-260

Jin-Soo Kim, Yarsun Hsu: Memory system behavior of Java programs: methodology and analysis. SIGMETRICS 2000: 264-274

Yarsun Hsu: Parallel Systems and Parallel I/O Technology. ICPADS 1997: 4

Peter F. Corbett, Dror G. Feitelson, Jean-Pierre Prost, George S. Almasi, Sandra Johnson Baylor, Anthony Bolmarcich, Yarsun Hsu, Julian Satran, Marc Snir, Robert Colao, Brian D. Herr, Joe Kavaky, Thomas R. Morgan, Anthony Zlotek: Parallel File Systems for the IBM SP Computers. IBM Systems Journal 34(2): 222-248 (1995)

Ching-Farn Eric Wu, Yarsun Hsu, Yew-Huey Liu: Efficient Stack Simulation for Set-Associative Virtual Address Cache with Real Tags. IEEE Trans. Computers 44(5): 719-723 (1995)

Sandra Johnson Baylor, Caroline Benveniste, Yarsun Hsu: Performance Evaluation of a Parallel I/O Architecture. International Conference on Supercomputing 1995: 404-413

Ching-Farn Eric Wu, Yew-Huey Liu, Yarsun Hsu: Timestamp consistency and trace-driven analysis for distributed parallel systems. IPPS 1995: 680-

Jesse Fang, Yarsun Hsu, Shing-Tsaan Huang, Jie-Yong Juang, W. H. Tsai, Horst Wedde: Are We Providing the Right Education for Computer Science/Engineering Students? ICPADS 1994: 14-15

Ching-Farn Eric Wu, Yarsun Hsu, Yew-Huey Liu: A Quantitative Evaluation of Cache Types for High-Performance Computer Systems. IEEE Trans. Computers 42(10): 1154-1162 (1993)

Ching-Farn Eric Wu, Yarsun Hsu, Yew-Huey Liu: Efficient Stack Simulation for Shared Memory Set-Associative Multiprocessor Caches. ICPP 1993: 163-170

Sandra Johnson Baylor, Yarsun Hsu: The Effects of Network Delays on the Performance of MIN-Based Cache Coherence Protocols. ICPP (1) 1991: 292-295

Sang Lyul Min, Yarsun Hsu, Hyoung-Joo Kim: A Design of Performance-optimized Control-based Synchronization. CONPAR 1990: 312-323