Jiang Hu

Huaizhi Su, Zhiping Wen, Feng Wang, Bowen Wei, Jiang Hu: Multifractal scaling behavior analysis for existing dams. Expert Syst. Appl. 40(12): 4922-4933 (2013)

Jiang Hu, Cheng-Kok Koh: Guest editorial: Special section on cross-domain physical optimization. IEEE Trans. on CAD of Integrated Circuits and Systems 32(2): 173-174 (2013)

Jiang Hu, Cheng-Kok Koh: Guest Editorial Special Section on the 2011 International Symposium on Physical Design. IEEE Trans. on CAD of Integrated Circuits and Systems 31(2): 165-166 (2012)

Muhammet Mustafa Ozdal, Steven M. Burns, Jiang Hu: Algorithms for Gate Sizing and Device Parameter Selection for High-Performance Designs. IEEE Trans. on CAD of Integrated Circuits and Systems 31(10): 1558-1571 (2012)

Kyu-Nam Shim, Jiang Hu: A low overhead built-in delay testing with voltage and frequency adaptation for variation resilience. DFT 2012: 170-177

Qiong Zhao, Jiang Hu: Track assignment considering crosstalk-induced performance degradation. ICCD 2012: 506-507

Jiang Hu, Cheng-Kok Koh (Eds.): International Symposium on Physical Design, ISPD'12, Napa, CA, USA, March 25-28, 2012. ACM 2012, isbn 978-1-4503-1167-0

Yifang Liu, Rupesh S. Shelar, Jiang Hu: Simultaneous Technology Mapping and Placement for Delay Minimization. IEEE Trans. on CAD of Integrated Circuits and Systems 30(3): 416-426 (2011)

Yifang Liu, Jiang Hu: GPU-Based Parallelization for Fast Circuit Optimization. ACM Trans. Design Autom. Electr. Syst. 16(3): 24 (2011)

Mohammad Asad R. Chaudhry, Zakia Asad, Alexander Sprintson, Jiang Hu: Efficient Congestion Mitigation Using Congestion-Aware Steiner Trees and Network Coding Topologies. VLSI Design 2011 (2011)

Muhammet Mustafa Ozdal, Steven M. Burns, Jiang Hu: Gate sizing and device technology selection algorithms for high-performance industrial designs. ICCAD 2011: 724-731

Xi Chen, Jiang Hu, Ning Xu: Regularity-constrained floorplanning for multi-core processors. ISPD 2011: 99-106

Yi-Le Huang, Jiang Hu, Weiping Shi: Lagrangian relaxation for gate implementation selection. ISPD 2011: 167-174

Kyu-Nam Shim, Jiang Hu: Transient and fine-grained voltage adaptation for variation resilience in VLSI interconnects. ISQED 2011: 80-86

Yimei Kang, Guan Wang, Jiang Hu: A mean shift based small target tracking algorithm in colored video. SoCPaR 2011: 407-412

Yao-Wen Chang, Jiang Hu (Eds.): Proceedings of the 2011 International Symposium on Physical Design, ISPD 2011, Santa Barbara, California, USA, March 27-30, 2011. ACM 2011, isbn 978-1-4503-0550-1

Yifang Liu, Jiang Hu: A New Algorithm for Simultaneous Gate Sizing and Threshold Voltage Assignment. IEEE Trans. on CAD of Integrated Circuits and Systems 29(2): 223-234 (2010)

Xiaoji Ye, Peng Li, Min Zhao, Rajendran Panda, Jiang Hu: Scalable Analysis of Mesh-Based Clock Distribution Networks Using Application-Specific Reduced Order Modeling. IEEE Trans. on CAD of Integrated Circuits and Systems 29(9): 1342-1353 (2010)

Ganesh Venkataraman, Zhuo Feng, Jiang Hu, Peng Li: Combinatorial Algorithms for Fast Clock Mesh Optimization. IEEE Trans. VLSI Syst. 18(1): 131-141 (2010)

Shiyan Hu, Patrik Shah, Jiang Hu: Pattern Sensitive Placement Perturbation for Manufacturability. IEEE Trans. VLSI Syst. 18(6): 1002-1006 (2010)

Rupak Samanta, Jiang Hu, Peng Li: Discrete Buffer and Wire Sizing for Link-Based Non-Tree Clock Networks. IEEE Trans. VLSI Syst. 18(7): 1025-1035 (2010)

Weixiang Shen, Yici Cai, Xianlong Hong, Jiang Hu: An Effective Gated Clock Tree Design Based on Activity and Register Aware Placement. IEEE Trans. VLSI Syst. 18(12): 1639-1648 (2010)

Yaoguang Wei, Jiang Hu, Frank Liu, Sachin S. Sapatnekar: Physical design techniques for optimizing RTA-induced variations. ASP-DAC 2010: 745-750

Tanuj Jindal, Charles J. Alpert, Jiang Hu, Zhuo Li, Gi-Joon Nam, Charles B. Winn: Detecting tangled logic structures in VLSI netlists. DAC 2010: 603-608

Fan Yang, Yici Cai, Qiang Zhou, Jiang Hu: SAT based multi-net rip-up-and-reroute for manufacturing hotspot removal. DATE 2010: 1369-1372

Yifang Liu, Yu Yang, Jiang Hu: Clustering-based simultaneous task and voltage scheduling for NoC systems. ICCAD 2010: 277-283

Venkata Rajesh Mekala, Yifang Liu, Xiaoji Ye, Jiang Hu, Peng Li: Accurate clock mesh sizing via sequential quadraticprogramming. ISPD 2010: 135-142

Kyu-Nam Shim, Jiang Hu, José Silva-Martínez: A dual-level adaptive supply voltage system for variation resilience. ISQED 2010: 38-43

Weixiang Shen, Yici Cai, Wei Chen, Yongqiang Lu, Qiang Zhou, Jiang Hu: Useful clock skew optimization under a multi-corner multi-mode design framework. ISQED 2010: 62-68

Weixiang Shen, Yici Cai, Xianlong Hong, Jiang Hu, Bing Lu: A single layer zero skew clock routing in X architecture. Science in China Series F: Information Sciences 52(8): 1466-1475 (2009)

Shiyan Hu, Jiang Hu: A fast general slew constrained minimum cost buffering algorithm. Microelectronics Journal 40(10): 1482-1486 (2009)

Shiyan Hu, Mahesh Ketkar, Jiang Hu: Gate Sizing for Cell-Library-Based Designs. IEEE Trans. on CAD of Integrated Circuits and Systems 28(6): 818-825 (2009)

Yang Liu, Tong Zhang, Jiang Hu: Design of Voltage Overscaled Low-Power Trellis Decoders in Presence of Process Variations. IEEE Trans. VLSI Syst. 17(3): 439-443 (2009)

Rupak Samanta, Ganesh Venkataraman, Jiang Hu: Clock Buffer Polarity Assignment for Power Noise Reduction. IEEE Trans. VLSI Syst. 17(6): 770-780 (2009)

Yifang Liu, Jiang Hu: GPU-based parallelization for fast circuit optimization. DAC 2009: 943-946

Pratik J. Shah, Jiang Hu: Impact of lithography-friendly circuit layout. ACM Great Lakes Symposium on VLSI 2009: 385-388

Yifang Liu, Jiang Hu: A new algorithm for simultaneous gate sizing and threshold voltage assignment. ISPD 2009: 27-34

Weixiang Shen, Yici Cai, Xianlong Hong, Jiang Hu: Low Power Gated Clock Tree Driven Placement. IEICE Transactions 91-A(2): 595-603 (2008)

Ke Cao, Jiang Hu: ASIC design flow considering lithography-induced effects. IET Circuits, Devices & Systems 2(1): 23-29 (2008)

Weixiang Shen, Yici Cai, Xianlong Hong, Jiang Hu, Bing Lu: Zero skew clock routing in X-architecture based on an improved greedy matching algorithm. Integration 41(3): 426-438 (2008)

Cheng Zhuo, Jiang Hu, Min Zhao, Kangsheng Chen: Power Grid Analysis and Optimization Using Algebraic Multigrid. IEEE Trans. on CAD of Integrated Circuits and Systems 27(4): 738-751 (2008)

Uday Padmanabhan, Janet Meiling Wang, Jiang Hu: Robust Clock Tree Routing in the Presence of Process Variations. IEEE Trans. on CAD of Integrated Circuits and Systems 27(8): 1385-1397 (2008)

Yifang Liu, Jiang Hu, Weiping Shi: Buffering Interconnect for Multicore Processor Designs. IEEE Trans. on CAD of Integrated Circuits and Systems 27(12): 2183-2196 (2008)

Yanfeng Wang, Qiang Zhou, Yici Cai, Jiang Hu, Xianlong Hong, Jinian Bian: Low power clock buffer planning methodology in F-D placement for large scale circuit design. ASP-DAC 2008: 370-375

Sridhar Varadan, Janet Meiling Wang, Jiang Hu: Handling partial correlations in yield prediction. ASP-DAC 2008: 543-548

Nimay Shah, Rupak Samanta, Ming Zhang, Jiang Hu, Duncan Walker: Built-In Proactive Tuning System for Circuit Aging Resilience. DFT 2008: 96-104

Yifang Liu, Rupesh S. Shelar, Jiang Hu: Delay-optimal simultaneous technology mapping and placement with applications to timing optimization. ICCAD 2008: 101-106

Weixiang Shen, Yici Cai, Xianlong Hong, Jiang Hu: Gate planning during placement for gated clock network. ICCD 2008: 128-133

Yifang Liu, Jiang Hu, Weiping Shi: Multi-scenario buffer insertion in multi-core processor designs. ISPD 2008: 15-22

Rupak Samanta, Jiang Hu, Peng Li: Discrete buffer and wire sizing for link-based non-tree clock networks. ISPD 2008: 175-181

Weixiang Shen, Yici Cai, Xianlong Hong, Jiang Hu: Activity and register placement aware gated clock network design. ISPD 2008: 182-189

Rupak Samanta, Ganesh Venkataraman, Nimay Shah, Jiang Hu: Elastic Timing Scheme for Energy-Efficient and Robust Performance. ISQED 2008: 537-542

Xiaoji Ye, Min Zhao, Rajendran Panda, Peng Li, Jiang Hu: Accelerating Clock Mesh Simulation Using Matrix-Level Macromodels and Dynamic Time Step Rounding. ISQED 2008: 627-632

Bor-Yiing Su, Yao-Wen Chang, Jiang Hu: An Exact Jumper-Insertion Algorithm for Antenna Violation Avoidance/Fixing Considering Routing Obstacles. IEEE Trans. on CAD of Integrated Circuits and Systems 26(4): 719-733 (2007)

Chin Ngai Sze, Charles J. Alpert, Jiang Hu, Weiping Shi: Path-Based Buffer Insertion. IEEE Trans. on CAD of Integrated Circuits and Systems 26(7): 1346-1355 (2007)

Shiyan Hu, Charles J. Alpert, Jiang Hu, Shrirang K. Karandikar, Zhuo Li, Weiping Shi, Chin Ngai Sze: Fast Algorithms for Slew-Constrained Minimum Cost Buffering. IEEE Trans. on CAD of Integrated Circuits and Systems 26(11): 2009-2022 (2007)

Ganesh Venkataraman, Jiang Hu, Frank Liu: Integrated Placement and Skew Optimization for Rotary Clocking. IEEE Trans. VLSI Syst. 15(2): 149-158 (2007)

Shiyan Hu, Qiuyang Li, Jiang Hu, Peng Li: Utilizing Redundancy for Timing Critical Interconnect. IEEE Trans. VLSI Syst. 15(10): 1067-1080 (2007)

Ke Cao, Jiang Hu, Mosong Cheng: Wire Sizing and Spacing for Lithographic Printability and Timing Optimization. IEEE Trans. VLSI Syst. 15(12): 1332-1340 (2007)

Bao Liu, Andrew B. Kahng, Xu Xu, Jiang Hu, Ganesh Venkataraman: A Global Minimum Clock Distribution Network Augmentation Algorithm for Guaranteed Clock Skew Yield. ASP-DAC 2007: 24-31

Jiang Hu, Andi Winterboer, Clifford Nass, Johanna D. Moore, Rebecca Illowsky: Context & usability testing: user-modeled information presentation in easy and difficult driving conditions. CHI 2007: 1343-1346

Shiyan Hu, Mahesh Ketkar, Jiang Hu: Gate Sizing For Cell Library-Based Designs. DAC 2007: 847-852

Shiyan Hu, Jiang Hu: Unified adaptivity optimization of clock and logic signals. ICCAD 2007: 125-130

Cheng Zhuo, Huafeng Zhang, Rupak Samanta, Jiang Hu, Kangsheng Chen: Modeling, optimization and control of rotary traveling-wave oscillator. ICCAD 2007: 476-480

Xiaoji Ye, Peng Li, Min Zhao, Rajendran Panda, Jiang Hu: Analysis of large clock meshes via harmonic-weighted model order reduction and port sliding. ICCAD 2007: 627-631

Andi Winterboer, Jiang Hu, Johanna D. Moore, Clifford Nass: The influence of user tailoring and cognitive load on user performance in spoken dialogue systems. INTERSPEECH 2007: 2717-2720

Shiyan Hu, Jiang Hu: Pattern sensitive placement for manufacturability. ISPD 2007: 27-34

Zhanyuan Jiang, Shiyan Hu, Jiang Hu, Weiping Shi: An Efficient Algorithm for RLC Buffer Insertion. ISQED 2007: 171-175

Weixiang Shen, Yici Cai, Xianlong Hong, Jiang Hu, Bing Lu: Planar-CRX: A Single-Layer Zero Skew Clock Routing in X-Architecture. ISQED 2007: 299-304

Yang Liu, Tong Zhang, Jiang Hu: Soft Clock Skew Scheduling for Variation-Tolerant Signal Processing Circuits: A Case Study of Viterbi Decoders. ISQED 2007: 749-754

Weixiang Shen, Yici Cai, Xianlong Hong, Jiang Hu: Activity-Aware Registers Placement for Low Power Gated Clock Tree Construction. ISVLSI 2007: 383-388

Ganesh Venkataraman, Jiang Hu: A Placement Methodology for Robust Clocking. VLSI Design 2007: 881-886

Di Wu, Jiang Hu, Rabi N. Mahapatra: Antenna Avoidance in Layer Assignment. IEEE Trans. on CAD of Integrated Circuits and Systems 25(4): 734-738 (2006)

Charles J. Alpert, Jiang Hu, Sachin S. Sapatnekar, Cliff C. N. Sze: Accurate estimation of global buffer delay within a floorplan. IEEE Trans. on CAD of Integrated Circuits and Systems 25(6): 1140-1145 (2006)

Anand Rajaram, Jiang Hu, Rabi N. Mahapatra: Reducing clock skew variability via crosslinks. IEEE Trans. on CAD of Integrated Circuits and Systems 25(6): 1176-1182 (2006)

Anand Rajaram, Bing Lu, Jiang Hu, Rabi N. Mahapatra, Wei Guo: Analytical bound for unwanted clock skew due to wire width variation. IEEE Trans. on CAD of Integrated Circuits and Systems 25(9): 1869-1876 (2006)

Mike Brzozowski, Kendra Carattini, Scott R. Klemmer, Patrick Mihelich, Jiang Hu, Andrew Y. Ng: groupTime: preference based group scheduling. CHI 2006: 1047-1056

Jamie Pearson, Jiang Hu, Holly P. Branigan, Martin J. Pickering, Clifford Nass: Adaptive language behavior in HCI: how expectations and beliefs about a system affect users' word choice. CHI 2006: 1177-1180

Shiyan Hu, Charles J. Alpert, Jiang Hu, Shrirang K. Karandikar, Zhuo Li, Weiping Shi, Cliff C. N. Sze: Fast algorithms for slew constrained minimum cost buffering. DAC 2006: 308-313

Shiyan Hu, Qiuyang Li, Jiang Hu, Peng Li: Steiner network construction for timing critical nets. DAC 2006: 379-384

Ke Cao, Sorin Dobre, Jiang Hu: Standard cell characterization considering lithography induced variations. DAC 2006: 801-804

Ganesh Venkataraman, Jiang Hu, Frank Liu, Cliff C. N. Sze: Integrated placement and skew optimization for rotary clocking. DATE 2006: 756-761

Min-Seok Kim, Jiang Hu: Associative skew clock routing for difficult instances. DATE 2006: 762-767

Cheng Zhuo, Jiang Hu, Min Zhao, Kangsheng Chen: Fast decap allocation based on algebraic multigrid. ICCAD 2006: 107-111

Zhanyuan Jiang, Shiyan Hu, Jiang Hu, Zhuo Li, Weiping Shi: A new RLC buffer insertion algorithm. ICCAD 2006: 553-557

Rupak Samanta, Ganesh Venkataraman, Jiang Hu: Clock buffer polarity assignment for power noise reduction. ICCAD 2006: 558-562

Ganesh Venkataraman, Zhuo Feng, Jiang Hu, Peng Li: Combinatorial algorithms for fast clock mesh optimization. ICCAD 2006: 563-567

Weixiang Shen, Yici Cai, Jiang Hu, Xianlong Hong, Bing Lu: High performance clock routing in X-architecture. ISCAS 2006

Bor-Yiing Su, Yao-Wen Chang, Jiang Hu: An optimal jumper insertion algorithm for antenna avoidance/fixing on general routing trees with obstacles. ISPD 2006: 56-63

Uday Padmanabhan, Janet Meiling Wang, Jiang Hu: Statistical clock tree routing for robustness to process variations. ISPD 2006: 149-156

Zhuo Feng, Peng Li, Jiang Hu: Efficient Model Update for General Link-Insertion Networks. ISQED 2006: 43-50

Cheng Zhuo, Jiang Hu, Kangsheng Chen: An Improved AMG-based Method for Fast Power Grid Analysis. ISQED 2006: 290-295

Yang Liu, Tong Zhang, Jiang Hu: Low Power Trellis Decoder with Overscaled Supply Voltage. SiPS 2006: 205-208

Yongqiang Lu, Chin Ngai Sze, Xianlong Hong, Qiang Zhou, Yici Cai, Liang Huang, Jiang Hu: Navigating Register Placement for Low Power Clock Network Design. IEICE Transactions 88-A(12): 3405-3411 (2005)

Rishi Chaturvedi, Jiang Hu: An efficient merging scheme for prescribed skew clock routing. IEEE Trans. VLSI Syst. 13(6): 750-754 (2005)

Zhuo Li, Cliff C. N. Sze, Charles J. Alpert, Jiang Hu, Weiping Shi: Making fast buffer insertion even faster via approximation techniques. ASP-DAC 2005: 13-18

Liang Huang, Yici Cai, Qiang Zhou, Xianlong Hong, Jiang Hu, Yongqiang Lu: Clock network minimization methodology based on incremental placement. ASP-DAC 2005: 99-102

Ke Cao, Puneet Dhawan, Jiang Hu: Library cell layout with Alt-PSM compliance and composability. ASP-DAC 2005: 216-219

Yongqiang Lu, Cliff C. N. Sze, Xianlong Hong, Qiang Zhou, Yici Cai, Liang Huang, Jiang Hu: Register placement for low power clock network. ASP-DAC 2005: 588-593

Ganesh Venkataraman, Cliff C. N. Sze, Jiang Hu: Skew scheduling and clock routing for improved tolerance to process variations. ASP-DAC 2005: 594-599

Di Wu, Jiang Hu, Min Zhao, Rabi N. Mahapatra: Timing driven track routing considering coupling capacitance. ASP-DAC 2005: 1156-1159

Yongqiang Lu, Cliff C. N. Sze, Xianlong Hong, Qiang Zhou, Yici Cai, Liang Huang, Jiang Hu: Navigating registers in placement for clock network minimization. DAC 2005: 176-181

Cliff C. N. Sze, Charles J. Alpert, Jiang Hu, Weiping Shi: Path based buffer insertion. DAC 2005: 509-514

Di Wu, Ganesh Venkataraman, Jiang Hu, Quiyang Li, Rabi N. Mahapatra: DiCER: distributed and cost-effective redundancy for variation tolerance. ICCAD 2005: 393-397

Ganesh Venkataraman, Nikhil Jayakumar, Jiang Hu, Peng Li, Sunil P. Khatri, Anand Rajaram, Patrick McGuinness, Charles J. Alpert: Practical techniques to reduce skew and its variations in buffered clock networks. ICCAD 2005: 592-596

QianYing Wang, Clifford Nass, Jiang Hu: Natural Language Query vs. Keyword Search: Effects of Task Complexity on Search Performance, Participant Perceptions, and Preferences. INTERACT 2005: 106-116

Jiang Hu, Mike Brzozowski: Preference-Based Group Scheduling. INTERACT 2005: 990-993

Di Wu, Jiang Hu, Rabi N. Mahapatra: Coupling aware timing optimization and antenna avoidance in layer assignment. ISPD 2005: 20-27

Anand Rajaram, David Z. Pan, Jiang Hu: Improved algorithms for link-based non-tree clock networks for skew variability reduction. ISPD 2005: 55-62

QianYing Wang, Jiang Hu, Clifford Nass: Natural Language Interface Put in Perspective: Interaction of Search Method and Task Complexity. NLUCS 2005: 3-12

Charles J. Alpert, Chris C. N. Chu, Gopal Gandham, Milos Hrkic, Jiang Hu, Chandramouli V. Kashyap, Stephen T. Quay: Simultaneous driver sizing and buffer insertion using a delay penalty estimation technique. IEEE Trans. on CAD of Integrated Circuits and Systems 23(1): 136-141 (2004)

Charles J. Alpert, Gopal Gandham, Milos Hrkic, Jiang Hu, Stephen T. Quay, Cliff C. N. Sze: Porosity-aware buffered Steiner tree construction. IEEE Trans. on CAD of Integrated Circuits and Systems 23(4): 517-526 (2004)

Haihua Su, Jiang Hu, Sachin S. Sapatnekar, Sani R. Nassif: A methodology for the simultaneous design of supply and signal networks. IEEE Trans. on CAD of Integrated Circuits and Systems 23(12): 1614-1624 (2004)

Di Wu, Jiang Hu, Rabi N. Mahapatra, Min Zhao: Layer assignment for crosstalk risk minimization. ASP-DAC 2004: 159-162

Cliff C. N. Sze, Jiang Hu, Charles J. Alpert: A place and route aware buffered Steiner tree construction. ASP-DAC 2004: 355-360

Anand Rajaram, Jiang Hu, Rabi N. Mahapatra: Reducing clock skew variability via cross links. DAC 2004: 18-23

Charles J. Alpert, Milos Hrkic, Jiang Hu, Stephen T. Quay: Fast and flexible buffer trees that navigate the physical layout environment. DAC 2004: 24-29

V. Seth, Min Zhao, Jiang Hu: Exploiting level sensitive latches in wire pipelining. ICCAD 2004: 283-290

Charles J. Alpert, Jiang Hu, Sachin S. Sapatnekar, Cliff C. N. Sze: Accurate estimation of global buffer delay within a floorplan. ICCAD 2004: 706-711

Rishi Chaturvedi, Jiang Hu: Buffered Clock Tree for High Quality IC Design. ISQED 2004: 381-386

Jiang Hu, Charles J. Alpert, Stephen T. Quay, Gopal Gandham: Buffer insertion with adaptive blockage avoidance. IEEE Trans. on CAD of Integrated Circuits and Systems 22(4): 492-498 (2003)

Charles J. Alpert, Jiang Hu, Sachin S. Sapatnekar, Paul Villarrubia: A practical methodology for early buffer and wire resource allocation. IEEE Trans. on CAD of Integrated Circuits and Systems 22(5): 573-583 (2003)

Anand Rajaram, Bing Lu, Wei Guo, Rabi N. Mahapatra, Jiang Hu: Analytical Bound for Unwanted Clock Skew due to Wire Width Variation. ICCAD 2003: 401-407

Rishi Chaturvedi, Jiang Hu: A Simple Yet Effective Merging Scheme for Prescribed-Skew Clock Routing. ICCD 2003: 282-

Charles J. Alpert, Gopal Gandham, Milos Hrkic, Jiang Hu, Stephen T. Quay: Porosity aware buffered steiner tree construction. ISPD 2003: 158-165

Bing Lu, Jiang Hu, Gary Ellis, Haihua Su: Process variation aware clock tree routing. ISPD 2003: 174-181

Jiang Hu, Sachin S. Sapatnekar: A timing-constrained simultaneous global routing algorithm. IEEE Trans. on CAD of Integrated Circuits and Systems 21(9): 1025-1036 (2002)

Haihua Su, Jiang Hu, Sachin S. Sapatnekar, Sani R. Nassif: Congestion-driven codesign of power and signal networks. DAC 2002: 64-69

Jiang Hu, Charles J. Alpert, Stephen T. Quay, Gopal Gandham: Buffer insertion with adaptive blockage avoidance. ISPD 2002: 92-97

Charles J. Alpert, Chris C. N. Chu, Gopal Gandham, Milos Hrkic, Jiang Hu, Chandramouli V. Kashyap, Stephen T. Quay: Simultaneous driver sizing and buffer insertion using a delay penalty estimation technique. ISPD 2002: 104-109

Jiang Hu, Sachin S. Sapatnekar: A survey on multi-net global routing for integrated circuits. Integration 31(1): 1-49 (2001)

Charles J. Alpert, Gopal Gandham, Jiang Hu, José Luis Neves, Stephen T. Quay, Sachin S. Sapatnekar: Steiner tree optimization for buffers, blockages, and bays. IEEE Trans. on CAD of Integrated Circuits and Systems 20(4): 556-562 (2001)

Charles J. Alpert, Jiang Hu, Sachin S. Sapatnekar, Paul Villarrubia: A Practical Methodology for Early Buffer and Wire Resource Allocation. DAC 2001: 189-194

Jiang Hu, Sachin S. Sapatnekar: Performance Driven Global Routing Through Gradual Refinement. ICCD 2001: 481-483

Charles J. Alpert, Gopal Gandham, Jiang Hu, José Luis Neves, Stephen T. Quay, Sachin S. Sapatnekar: Steiner tree optimization for buffers. Blockages and bays. ISCAS (5) 2001: 399-402

Charles J. Alpert, Milos Hrkic, Jiang Hu, Andrew B. Kahng, John Lillis, Bao Liu, Stephen T. Quay, Sachin S. Sapatnekar, A. J. Sullivan, Paul Villarrubia: Buffered Steiner trees for difficult instances. ISPD 2001: 4-9

Jiang Hu, Sachin S. Sapatnekar: Algorithms for non-Hanan-based optimization for VLSI interconnectunder a higher-order AWE model. IEEE Trans. on CAD of Integrated Circuits and Systems 19(4): 446-458 (2000)

Jiang Hu, Sachin S. Sapatnekar: A Timing-Constrained Algorithm for Simultaneous Global Routing of Multiple Nets. ICCAD 2000: 99-103

Huibo Hou, Jiang Hu, Sachin S. Sapatnekar: Non-Hanan routing. IEEE Trans. on CAD of Integrated Circuits and Systems 18(4): 436-444 (1999)

Jiang Hu, Sachin S. Sapatnekar: FAR-DS: Full-Plane AWE Routing with Driver Sizing. DAC 1999: 84-89

Jiang Hu, Sachin S. Sapatnekar: Simultaneous buffer insertion and non-Hanan optimization for VLSI interconnect under a higher order AWE model. ISPD 1999: 133-138