Wen-Hsiang Hu

Chifeng Wang, Wen-Hsiang Hu, Nader Bagherzadeh: Scalable load balancing congestion-aware Network-on-Chip router architecture. J. Comput. Syst. Sci. 79(4): 421-439 (2013)

Chifeng Wang, Wen-Hsiang Hu, Nader Bagherzadeh: A load-balanced congestion-aware wireless network-on-chip design for multi-core platforms. Microprocessors and Microsystems - Embedded Hardware Design 36(7): 555-570 (2012)

Wen-Hsiang Hu, Chifeng Wang, Nader Bagherzadeh: Design and Analysis of a Mesh-based Wireless Network-on-Chip. PDP 2012: 483-490

Chifeng Wang, Wen-Hsiang Hu, Seung Eun Lee, Nader Bagherzadeh: Area and power-efficient innovative congestion-aware Network-on-Chip architecture. Journal of Systems Architecture - Embedded Systems Design 57(1): 24-38 (2011)

Chifeng Wang, Wen-Hsiang Hu, Nader Bagherzadeh: A Wireless Network-on-Chip Design for Multicore Platforms. PDP 2011: 409-416

Chifeng Wang, Wen-Hsiang Hu, Seung Eun Lee, Nader Bagherzadeh: Area and Power-efficient Innovative Network-on-Chip Architecurte. PDP 2010: 533-539

Jun Ho Bahn, Jungsook Yang, Wen-Hsiang Hu, Nader Bagherzadeh: Parallel FFT Algorithms on Network-on-Chips. Journal of Circuits, Systems, and Computers 18(2): 255-269 (2009)

Wen-Hsiang Hu, Jun Ho Bahn, Nader Bagherzadeh: Parallel LDPC Decoding on a Network-on-Chip Based Multiprocessor Platform. SBAC-PAD 2009: 35-40

Chun-Ming Huang, Kuen-Jong Lee, Chih-Chyau Yang, Wen-Hsiang Hu, Shi-Shen Wang, Jeng-Bin Chen, Chi-Shi Chen, Lan-Da Van, Chien-Ming Wu, Wei-Chang Tsai, Jing-Yang Jou: Multi-Project System-on-Chip (MP-SoC): A Novel Test Vehicle for SoC Silicon Prototyping. SoCC 2006: 137-140

Lan-Da Van, Hsin-Fu Luo, Chien-Ming Wu, Wen-Hsiang Hu, Chun-Ming Huang, Wei-Chang Tsai: A high-performance area-aware DSP processor architecture for video codecs. ICME 2004: 1499-1502