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Chung-Yang Huang
Chung-Yang (Ric) Huang
2010 – today
- 2013
[j5]Shao-Lun Huang, Wei-Hsun Lin, Po-Kai Huang, Chung-Yang Huang: Match and Replace: A Functional ECO Engine for Multierror Circuit Rectification. IEEE Trans. on CAD of Integrated Circuits and Systems 32(3): 467-478 (2013)- [j4]Yu-Fu Yeh, Hsin-Cheng Lin, Chung-Yang Huang: An Ultrasynchronization Checking Method With Trace-Driven Simulation for Fast and Accurate MPSoC Virtual Platform Simulation. IEEE Trans. on CAD of Integrated Circuits and Systems 32(6): 928-939 (2013)
- [c31]Cheng-Yin Wu, Chi-An Wu, Chien-Yu Lai, Chung-Yang (Ric) Huang: A counterexample-guided interpolant generation algorithm for SAT-based model checking. DAC 2013: 118
- [c30]
- 2012
- [c29]Shihheng Tsai, Man-Yu Li, Chung-Yang Huang: A semi-formal min-cost buffer insertion technique considering multi-mode multi-corner timing constraints. ASP-DAC 2012: 505-510
- [c28]Chun-Nan Chou, Yen-Sheng Ho, Chiao Hsieh, Chung-Yang (Ric) Huang: Symbolic model checking on SystemC designs. DAC 2012: 327-333
- [c27]Kai-Fu Tang, Po-Kai Huang, Chun-Nan Chou, Chung-Yang Huang: Multi-patch generation for multi-error logic rectification by interpolation with cofactor reduction. DATE 2012: 1567-1572
- [c26]Bo-Han Wu, Chung-Yang (Ric) Huang: A robust general constrained random pattern generator for constraints with variable ordering. ICCAD 2012: 109-114
- [c25]Hu-Hsi Yeh, Cheng-Yin Wu, Chung-Yang (Ric) Huang: QuteRTL: Towards an Open Source Framework for RTL Design Synthesis and Verification. TACAS 2012: 377-391
- 2011
- [c24]Chung-Yang Huang, Yu-Fan Yin, Chih-Jen Hsu, Thomas B. Huang, Ting-Mao Chang: SoC HW/SW verification and validation. ASP-DAC 2011: 297-300
- [c23]Shao-Lun Huang, Chi-An Wu, Kai-Fu Tang, Chang-Hong Hsu, Chung-Yang Huang: A robust ECO engine by resource-constraint-aware technology mapping and incremental routing optimization. ASP-DAC 2011: 382-387
- [c22]Kai-Fu Tang, Chi-An Wu, Po-Kai Huang, Chung-Yang (Ric) Huang: Interpolation-based incremental ECO synthesis for multi-error logic rectification. DAC 2011: 146-151
- [c21]Ting-Hao Lin, Chung-Yang (Ric) Huang: Using SAT-based Craig interpolation to enlarge clock gating functions. DAC 2011: 621-626
- [c20]Yu-Fu Yeh, Chung-Yang Huang, Chi-An Wu, Hsin-Cheng Lin: Speeding Up MPSoC virtual platform simulation by Ultra Synchronization Checking Method. DATE 2011: 353-358
- [c19]Shao-Lun Huang, Wei-Hsun Lin, Chung-Yang (Ric) Huang: Match and replace - A functional ECO engine for multi-error circuit rectification. ICCAD 2011: 383-388
- [c18]Bo-Han Wu, Chun-Ju Yang, Chia-Cheng Tso, Chung-Yang (Ric) Huang: Toward an extremely-high-throughput and even-distribution pattern generator for the constrained random simulation techniques. ICCAD 2011: 602-607
- [c17]Hu-Hsi Yeh, Cheng-Yin Wu, Chung-Yang (Ric) Huang: Property-specific sequential invariant extraction for SAT-based unbounded model checking. ICCAD 2011: 674-678
- 2010
- [j3]Jie-Hong Roland Jiang, Chih-Chun Lee, Alan Mishchenko, Chung-Yang Huang: To SAT or Not to SAT: Scalable Exploration of Functional Dependency. IEEE Trans. Computers 59(4): 457-467 (2010)
- [c16]Kuen-Huei Lin, Siao-Jie Cai, Chung-Yang (Ric) Huang: Speeding up SoC virtual platform simulation by data-dependency-aware synchronization and scheduling. ASP-DAC 2010: 143-148
- [c15]Hu-Hsi Yeh, Chung-Yang Huang: Automatic constraint generation for guided random simulation. ASP-DAC 2010: 613-618
- [c14]Jing-Jia Nian, Shihgeng Tsai, Chung-Yang (Ric) Huang: A unified multi-corner multi-mode static timing analysis engine. ASP-DAC 2010: 669-674
- [c13]Bo-Han Wu, Chun-Ju Yang, Chung-Yang Huang, Jie-Hong Roland Jiang: A robust functional ECO engine by SAT proof minimization and interpolation techniques. ICCAD 2010: 729-734
- [c12]Chun-Nan Chou, Chang-Hong Hsu, Yueh-Tung Chao, Chung-Yang Huang: Formal deadlock checking on high-level SystemC designs. ICCAD 2010: 794-799
2000 – 2009
- 2009
- [c11]Chi-An Wu, Ting-Hao Lin, Shao-Lun Huang, Chung-Yang Huang: SAT-controlled redundancy addition and removal: a novel circuit restructuring technique. ASP-DAC 2009: 191-196
- [c10]Shihheng Tsai, Chung-Yang Huang: A false-path aware formal static timing analyzer considering simultaneous input transitions. DAC 2009: 25-30
- [c9]Chih-Jen Hsu, Shao-Lun Huang, Chi-An Wu, Chung-Yang Huang: Interpolant generation without constructing resolution graph. ICCAD 2009: 9-12
- 2008
- [c8]Chao-Yue Lai, Chung-Yang Huang, Kei-Yong Khoo: Improving Constant-Coefficient Multiplier Verification by Partial Product Identification. DATE 2008: 813-818
- 2007
- [c7]Chi-An Wu, Ting-Hao Lin, Chih-Chun Lee, Chung-Yang Huang: QuteSAT: a robust circuit-based SAT solver for complex circuit structure. DATE 2007: 1313-1318
- [c6]Chih-Chun Lee, Jie-Hong Roland Jiang, Chung-Yang Huang, Alan Mishchenko: Scalable exploration of functional dependency by interpolation and incremental SAT solving. ICCAD 2007: 227-233
- [c5]Hsing-Chih Hung, Ting-Hao Lin, Chung-Yang Huang: QuteIP: An IP qualification framework for System on Chip. SoCC 2007: 237-240
- 2001
- [j2]Chung-Yang Huang, Kwang-Ting Cheng: Using word-level ATPG and modular arithmetic constraint-solvingtechniques for assertion property checking. IEEE Trans. on CAD of Integrated Circuits and Systems 20(3): 381-391 (2001)
- [c4]Ganapathy Parthasarathy, Chung-Yang Huang, Kwang-Ting Cheng: An analysis of ATPG and SAT algorithms for formal verification. HLDVT 2001: 177-182
- 2000
- [j1]Shi-Yu Huang, Kwang-Ting Cheng, Kuang-Chien Chen, Chung-Yang Huang, Forrest Brewer: AQUILA: An Equivalence Checking System for Large Sequential Designs. IEEE Trans. Computers 49(5): 443-464 (2000)
- [c3]Chung-Yang Huang, Kwang-Ting Cheng: Assertion checking by combined word-level ATPG and modular arithmetic constraint-solving techniques. DAC 2000: 118-123
- [c2]Chung-Yang Huang, Bwolen Yang, Huan-Chih Tsai, Kwang-Ting Cheng: Static property checking using ATPG vs. BDD techniques. ITC 2000: 309-316
1990 – 1999
- 1998
- [c1]Chung-Yang Huang, Yucheng Wang, Kwang-Ting Cheng: LIBRA - a library-independent framework for post-layout performance optimization. ISPD 1998: 135-140
Coauthor Index
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last updated on 2013-05-28 21:40 CEST by the dblp team