Jing-Reng Huang

Chih-Yen Lo, Chen-Hsing Wang, Kuo-Liang Cheng, Jing-Reng Huang, Chih-Wea Wang, Shin-Moe Wang, Cheng-Wen Wu: STEAC: A Platform for Automatic SOC Test Integration. IEEE Trans. VLSI Syst. 15(5): 541-545 (2007)

Ming-Jun Hsiao, Jing-Reng Huang, Tsin-Yuan Chang: A Built-In Parametric Timing Measurement Unit. IEEE Design & Test of Computers 21(4): 322-330 (2004)

Kuo-Liang Cheng, Jing-Reng Huang, Chih-Wea Wang, Chih-Yen Lo, Li-Ming Denq, Chih-Tsun Huang, Shin-Wei Hung, Jye-Yuan Lee: An SOC Test Integration Platform and Its Industrial Realization. ITC 2004: 1213-1222

Chih-Wea Wang, Jing-Reng Huang, Yen-Fu Lin, Kuo-Liang Cheng, Chih-Tsun Huang, Cheng-Wen Wu, Youn-Long Lin: Test Scheduling of BISTed Memory Cores for SOC. Asian Test Symposium 2002: 356-

Huan-Shan Hsu, Jing-Reng Huang, Kuo-Liang Cheng, Chih-Wea Wang, Chih-Tsun Huang, Cheng-Wen Wu, Youn-Long Lin: Test Scheduling and Test Access Architecture Optimization for System-on-Chip. Asian Test Symposium 2002: 411-

Horng-Bin Wang, Shi-Yu Huang, Jing-Reng Huang: Gate-Delay Fault Diagnosis Using the Inject-and-Evaluate Paradigm. DFT 2002: 117-128

Kuo-Liang Cheng, Chia-Ming Hsueh, Jing-Reng Huang, Jen-Chieh Yeh, Chih-Tsun Huang, Cheng-Wen Wu: Automatic Generation of Memory Built-in Self-Test Cores for System-on-Chip. Asian Test Symposium 2001: 91-96

Ming-Jun Hsiao, Jing-Reng Huang, Shao-Shen Yang, Tsin-Yuan Chang: A low-cost CMOS time interval measurement core. ISCAS (4) 2001: 190-193

Ming-Jun Hsiao, Jing-Reng Huang, Shao-Shen Yang, Tsin-Yuan Chang: A built-in timing parametric measurement unit. ITC 2001: 315-322

Jing-Reng Huang, Madhu K. Iyer, Kwang-Ting Cheng: A Self-Test Methodology for IP Cores in Bus-Based Programmable SoCs. VTS 2001: 198-203

Wei-Cheng Lai, Jing-Reng Huang, Kwang-Ting (Tim) Cheng: Embedded-Software-Based Approach to Testing Crosstalk-Induced Faults at On-Chip Buses. VTS 2001: 204-209

Chih-Tsun Huang, Jing-Reng Huang, Cheng-Wen Wu: A programmable built-in self-test core for embedded memories. ASP-DAC 2000: 11-12

Jing-Reng Huang, Chee-Kian Ong, Kwang-Ting Cheng, Cheng-Wen Wu: An FPGA-based re-configurable functional tester for memory chips. Asian Test Symposium 2000: 51-57

Yea-Ling Horng, Jing-Reng Huang, Tsin-Yuan Chang: A realistic fault model for flash memories. Asian Test Symposium 2000: 274-281

Chuang Cheng, Chih-Tsun Huang, Jing-Reng Huang, Cheng-Wen Wu, Chen-Jong Wey, Ming-Chang Tsai: BRAINS: A BIST Compiler for Embedded Memories. DFT 2000: 299-

Chih-Tsun Huang, Jing-Reng Huang, Chi-Feng Wu, Cheng-Wen Wu, Tsin-Yuan Chang: A Programmable BIST Core for Embedded DRAM. IEEE Design & Test of Computers 16(1): 59-70 (1999)