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Po-Tsang Huang
2010 – today
- 2013
[c15]Chih-Wei Chang, Po-Tsang Huang, Lei-Chun Chou, Shang-Lin Wu, Shih-Wei Lee, Ching-Te Chuang, Kuan-Neng Chen, Jin-Chern Chiou, Wei Hwang, Yen-Chi Lee, Chung-Hsi Wu, Kuo-Hua Chen, Chi-Tsung Chiu, Ho-Ming Tong: Through-silicon-via-based double-side integrated microsystem for neural sensing applications. ISSCC 2013: 102-103- 2012
- [j4]Po-Tsang Huang, Wei Hwang: Self-Calibrated Energy-Efficient and Reliable Channels for On-Chip Interconnection Networks. J. Electrical and Computer Engineering 2012 (2012)
- [c14]Po-Jen Yang, Po-Tsang Huang, Wei Hwang: Substrate noise suppression technique for power integrity of TSV 3D integration. ISCAS 2012: 3274-3277
- [c13]Tzu-Ting Chiang, Po-Tsang Huang, Ching-Te Chuang, Kuan-Neng Chen, Jin-Chern Chiou, Kuo-Hua Chen, Chi-Tsung Chiu, Ho-Ming Tong, Wei Hwang: On-chip self-calibrated process-temperature sensor for TSV 3D integration. SoCC 2012: 370-375
- 2011
- [j3]Po-Tsang Huang, Wei Hwang: Two-Level FIFO Buffer Design for Routers in On-Chip Interconnection Networks. IEICE Transactions 94-A(11): 2412-2424 (2011)
- [j2]Po-Tsang Huang, Wei Hwang: A 65 nm 0.165 fJ/Bit/Search 256 , ˟, 144 TCAM Macro Design for IPv6 Lookup Tables. J. Solid-State Circuits 46(2): 507-519 (2011)
- [c12]Po-Tsang Huang, Yung Chang, Wei Hwang: On-demand memory sub-system for multi-core SoCs. SoCC 2011: 122-127
- 2010
- [j1]Po-Tsang Huang, Xin-Ru Lee, Hsie-Chia Chang, Chen-Yi Lee, Wei Hwang: A Low Power Differential Cascode Voltage Switch with Pass Gate Pulsed Latch for Viterbi Decoder. J. Low Power Electronics 6(4): 551-562 (2010)
- [c11]Hsin Rau, Chien-Hung Wu, Wei-Jung Shiang, Po-Tsang Huang: A decision support system of statistical process control for printed circuit boards manufacturing. ICMLC 2010: 2454-2458
- [c10]Tien-Hung Lin, Po-Tsang Huang, Wei Hwang: Power noise suppression technique using active decoupling capacitor for TSV 3D integration. SoCC 2010: 209-212
2000 – 2009
- 2009
- [c9]
- 2008
- [c8]Po-Tsang Huang, Shu-Wei Chang, Wen-Yen Liu, Wei Hwang: "Green" micro-architecture and circuit co-design for ternary content addressable memory. ISCAS 2008: 3322-3325
- [c7]Li-Pu Chuang, Ming-Hung Chang, Po-Tsang Huang, Chih-Hao Kan, Wei Hwang: A 5.2mW all-digital fast-lock self-calibrated multiphase delay-locked loop. ISCAS 2008: 3342-3345
- [c6]Po-Tsang Huang, Wei-Li Fang, Yin-Ling Wang, Wei Hwang: Low Power and Reliable Interconnection with Self-Corrected Green Coding Scheme for Network-on-Chip. NOCS 2008: 77-83
- [c5]Mu-Tien Chang, Po-Tsang Huang, Wei Hwang: A robust ultra-low power asynchronous FIFO memory with self-adaptive power control. SoCC 2008: 175-178
- 2007
- [c4]Mu-Tien Chang, Po-Tsang Huang, Wei Hwang: A 65nm low power 2T1D embedded DRAM with leakage current reduction. SoCC 2007: 207-210
- 2006
- [c3]Jen-Wei Yang, Po-Tsang Huang, Wei Hwang: On-Chip DC-DC Converter with Frequency Detector for Dynamic Voltage Scaling Technology. APCCAS 2006: 666-669
- [c2]Po-Tsang Huang, Wei-Keng Chang, Wei Hwang: Low Power Pre-Comparison Scheme for NOR-Type 10T Content Addressable Memory. APCCAS 2006: 1301-1304
- [c1]Po-Tsang Huang, Wei Hwang: 2-level FIFO architecture design for switch fabrics in network-on-chip. ISCAS 2006
Coauthor Index
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last updated on 2013-04-09 21:27 CEST by the dblp team