Rei-Fu Huang

Chen-Wei Lin, Hung-Hsin Chen, Hao-Yu Yang, Chin-Yuan Huang, Mango Chia-Tso Chao, Rei-Fu Huang: Fault Models and Test Methods for Subthreshold SRAMs. IEEE Trans. Computers 62(3): 468-481 (2013)

Hao-Yu Yang, Chi-Min Chang, Mango Chia-Tso Chao, Rei-Fu Huang, Shih-Chin Lin: Testing Methodology of Embedded DRAMs. IEEE Trans. VLSI Syst. 20(9): 1715-1728 (2012)

Rei-Fu Huang, Hao-Yu Yang, Mango Chia-Tso Chao, Shih-Chin Lin: Alternate hammering test for application-specific DRAMs and an industrial case study. DAC 2012: 1012-1017

Chin-Lung Su, Rei-Fu Huang, Cheng-Wen Wu, Kun-Lun Luo, Wen Ching Wu: A Built-in Self-Diagnosis and Repair Design With Fail Pattern Identification for Memories. IEEE Trans. VLSI Syst. 19(12): 2184-2194 (2011)

Chen-Wei Lin, Hung-Hsin Chen, Hao-Yu Yang, Mango Chia-Tso Chao, Rei-Fu Huang: Fault models and test methods for subthreshold SRAMs. ITC 2010: 427-436

Mango Chia-Tso Chao, Hao-Yu Yang, Rei-Fu Huang, Shih-Chin Lin, Ching-Yu Chin: Fault models for embedded-DRAM macros. DAC 2009: 714-719

Chi-Min Chang, Mango Chia-Tso Chao, Rei-Fu Huang, Ding-Yuan Chen: Testing Methodology of Embedded DRAMs. ITC 2008: 1-9

Rei-Fu Huang, Chao-Hsun Chen, Cheng-Wen Wu: Economic Aspects of Memory Built-in Self-Repair. IEEE Design & Test of Computers 24(2): 164-172 (2007)

Rei-Fu Huang, Jin-Fu Li, Jen-Chieh Yeh, Cheng-Wen Wu: Raisin: Redundancy Analysis Algorithm Simulation. IEEE Design & Test of Computers 24(4): 386-396 (2007)

Jin-Fu Li, Jen-Chieh Yeh, Rei-Fu Huang, Cheng-Wen Wu: A built-in self-repair design for RAMs with 2-D redundancy. IEEE Trans. VLSI Syst. 13(6): 742-745 (2005)

Rei-Fu Huang, Yan-Ting Lai, Yung-Fa Chou, Cheng-Wen Wu: SRAM delay fault modeling and test algorithm development. ASP-DAC 2004: 104-109

Chih-Tsun Huang, Jen-Chieh Yeh, Yuan-Yuan Shih, Rei-Fu Huang, Cheng-Wen Wu: On Test and Diagnostics of Flash Memories. Asian Test Symposium 2004: 260-265

Rei-Fu Huang, Chin-Lung Su, Cheng-Wen Wu, Shen-Tien Lin, Kun-Lun Luo, Yeong-Jar Chang: Fail Pattern Identification for Memory Built-In Self-Repair. Asian Test Symposium 2004: 366-371

Chin-Lung Su, Rei-Fu Huang, Cheng-Wen Wu, Chien-Chung Hung, Ming-Jer Kao, Yeong-Jar Chang, Wen Ching Wu: MRAM Defect Analysis and Fault Modeli. ITC 2004: 124-133

Li-Ming Denq, Rei-Fu Huang, Cheng-Wen Wu, Yeong-Jar Chang, Wen Ching Wu: A Parallel Built-in Diagnostic Scheme for Multiple Embedded Memories. MTDT 2004: 65-69

Rei-Fu Huang, Yung-Fa Chou, Cheng-Wen Wu: Defect Oriented Fault Analysis for SRAM. Asian Test Symposium 2003: 256-261

Chin-Lung Su, Rei-Fu Huang, Cheng-Wen Wu: A Processor-Based Built-In Self-Repair Design for Embedded Memories. Asian Test Symposium 2003: 366-371

Jin-Fu Li, Jen-Chieh Yeh, Rei-Fu Huang, Cheng-Wen Wu, Peir-Yuan Tsai, Archer Hsu, Eugene Chow: A Built-In Self-Repair Scheme for Semiconductor Memories with 2-D Redundancy. ITC 2003: 393-402

Rei-Fu Huang, Li-Ming Denq, Cheng-Wen Wu, Jin-Fu Li: A Testability-Driven Optimizer and Wrapper Generator for Embedded Memories. MTDT 2003: 53-

Rei-Fu Huang, Jin-Fu Li, Jen-Chieh Yeh, Cheng-Wen Wu: A Simulator for E aluating Redundancy Analysis Algorithms of Repairable Embedded Memories. IOLTW 2002: 262-

Rei-Fu Huang, Jin-Fu Li, Jen-Chieh Yeh, Cheng-Wen Wu: A Simulator for Evaluating Redundancy Analysis Algorithms of Repairable Embedded Memories. MTDT 2002: 68-