Shi-Yu Huang

Yu-Hsiang Lin, Shi-Yu Huang, Kun-Han Tsai, Wu-Tung Cheng, Stephen K. Sunter, Yung-Fa Chou, Ding-Ming Kwai: Parametric Delay Test of Post-Bond Through-Silicon Vias in 3-D ICs via Variable Output Thresholding Analysis. IEEE Trans. on CAD of Integrated Circuits and Systems 32(5): 737-747 (2013)

Ji-Wei Ker, Shi-Yu Huang, Chao-Wen Tzeng, Ding-Ming Kwai, Yung-Fa Chou: Die-to-Die Clock Synchronization for 3-D IC Using Dual Locking Mechanism. IEEE Trans. on Circuits and Systems 60-I(4): 908-917 (2013)

Tsung-Yeh Li, Shi-Yu Huang, Hsuan-Jung Hsu, Chao-Wen Tzeng, Chih-Tsun Huang, Jing-Jia Liou, Hsi-Pin Ma, Po-Chiun Huang, Jenn-Chyou Bor, Ching-Cheng Tien, Chi-Hu Wang, Cheng-Wen Wu: AC-Plus Scan Methodology for Small Delay Testing and Characterization. IEEE Trans. VLSI Syst. 21(2): 329-341 (2013)

Jhih-Wei You, Shi-Yu Huang, Yu-Hsiang Lin, Meng-Hsiu Tsai, Ding-Ming Kwai, Yung-Fa Chou, Cheng-Wen Wu: In-Situ Method for TSV Delay Testing and Characterization Using Input Sensitivity Analysis. IEEE Trans. VLSI Syst. 21(3): 443-453 (2013)

Feng-Cheng Huang, Shi-Yu Huang, Ji-Wei Ker, Yung-Chang Chen: High-Performance SIFT Hardware Accelerator for Real-Time Image Feature Extraction. IEEE Trans. Circuits Syst. Video Techn. 22(3): 340-351 (2012)

Yu-Hsiang Lin, Shi-Yu Huang, Kun-Han Tsai, Wu-Tung Cheng: Programmable Leakage Test and Binning for TSVs. ATS 2012: 43-48

Shi-Yu Huang, Yu-Hsiang Lin, Kun-Han Tsai, Wu-Tung Cheng, Stephen K. Sunter, Yung-Fa Chou, Ding-Ming Kwai: Small delay testing for TSVs in 3-D ICs. DAC 2012: 1031-1036

Yu-Hsiang Lin, Shi-Yu Huang, Kun-Han Tsai, Wu-Tung Cheng, Stephen K. Sunter: A unified method for parametric fault characterization of post-bond TSVs. ITC 2012: 1-10

Shyue-Kung Lu, Yin Chen, Shi-Yu Huang, Cheng Wu: Speeding Up Emulation-Based Diagnosis Techniques for Logic Cores. IEEE Design & Test of Computers 28(4): 88-97 (2011)

Cheng-Hung Lo, Shi-Yu Huang: P-P-N Based 10T SRAM Cell for Low-Leakage and Resilient Subthreshold Operation. J. Solid-State Circuits 46(3): 695-704 (2011)

Hsuan-Jung Hsu, Shi-Yu Huang: A Low-Jitter ADPLL via a Suppressive Digital Filter and an Interpolation-Based Locking Scheme. IEEE Trans. VLSI Syst. 19(1): 165-170 (2011)

Chen-Wei Hsu, Jia-Lu Liao, Shan-Chien Fang, Chia-Chien Weng, Shi-Yu Huang, Wen-Tsan Hsieh, Jen-Chieh Yeh: PowerDepot: integrating IP-based power modeling with ESL power analysis for multi-core SoC designs. DAC 2011: 47-52

Chin-Fu Li, Chi-Ying Lee, Chen-Hsing Wang, Shu-Lin Chang, Li-Ming Denq, Chun-Chuan Chi, Hsuan-Jung Hsu, Ming-Yi Chu, Jing-Jia Liou, Shi-Yu Huang, Po-Chiun Huang, Hsi-Pin Ma, Jenn-Chyou Bor, Cheng-Wen Wu, Ching-Cheng Tien, Chi-Hu Wang, Yung-Sheng Kuo, Chih-Tsun Huang, Tien-Yu Chang: A low-cost wireless interface with no external antenna and crystal oscillator for cm-range contactless testing. DAC 2011: 771-776

Chun-Kai Tseng, Shi-Yu Huang, Chia-Chien Weng, Shan-Chien Fang, Ji-Jan Chen: Black-box leakage power modeling for cell library and SRAM compiler. DATE 2011: 637-642

Yi-Chung Chang, Shi-Yu Huang, Chao-Wen Tzeng, Jack T. Yao: A fully cell-based design for timing measurement of memory. ITC 2011: 1-10

Chao-Wen Tzeng, Shi-Yu Huang: Split-Masking: An Output Masking Scheme for Effective Compound Defect Diagnosis in Scan Architecture With Test Compression. IEEE Trans. on CAD of Integrated Circuits and Systems 29(5): 834-839 (2010)

Wen-Tsan Hsieh, Jen-Chieh Yeh, Shi-Yu Huang: PAC duo system power estimation at ESL. ASP-DAC 2010: 815-820

Jhih-Wei You, Shi-Yu Huang, Ding-Ming Kwai, Yung-Fa Chou, Cheng-Wen Wu: Performance Characterization of TSV in 3D IC via Sensitivity Analysis. Asian Test Symposium 2010: 389-394

Cheng-Yen Lin, Po-Yu Chen, Chun-Kai Tseng, Chung-Wen Huang, Chia-Chieh Weng, Chi-Bang Kuan, Shih-Han Lin, Shi-Yu Huang, Jenq Kuen Lee: Power aware SID-based simulator for embedded multicore DSP subsystems. CODES+ISSS 2010: 95-104

Chao-Wen Tzeng, Han-Chia Cheng, Shi-Yu Huang: Layout-Based Defect-Driven Diagnosis for Intracell Bridging Defects. IEEE Trans. on CAD of Integrated Circuits and Systems 28(5): 764-769 (2009)

Chao-Wen Tzeng, Shi-Yu Huang: QC-Fill: Quick-and-Cool X-Filling for Multicasting-Based Scan Test. IEEE Trans. on CAD of Integrated Circuits and Systems 28(11): 1756-1766 (2009)

Chao-Wen Tzeng, Shi-Yu Huang: QC-Fill: An X-Fill method for quick-and-cool scan test. DATE 2009: 1142-1147

Chao-Wen Tzeng, Shi-Yu Huang: UMC-Scan Test Methodology: Exploiting the Maximum Freedom of Multicasting. IEEE Design & Test of Computers 25(2): 132-140 (2008)

Ya-Chun Lai, Shi-Yu Huang: A Resilient and Power-Efficient Automatic-Power-Down Sense Amplifier for SRAM Design. IEEE Trans. on Circuits and Systems 55-II(10): 1031-1035 (2008)

Shin-Pao Cheng, Shi-Yu Huang: A low-power SRAM for Viterbi decoder in wireless communication. IEEE Trans. Consumer Electronics 54(2): 290-295 (2008)

Chao-Wen Tzeng, Jheng-Syun Yang, Shi-Yu Huang: A versatile paradigm for scan chain diagnosis of complex faults using signal processing techniques. ACM Trans. Design Autom. Electr. Syst. 13(1) (2008)

Chao-Wen Tzeng, J.-J. Hsu, Shi-Yu Huang: Robust paradigm for diagnosing hold-time faults in scan chains. IET Computers & Digital Techniques 1(6): 706-715 (2007)

Chia-Chien Weng, Ching-Shang Yang, Shi-Yu Huang: RT-level vector selection for realistic peak power simulation. ACM Great Lakes Symposium on VLSI 2007: 576-581

Yu-Chiun Lin, Shi-Yu Huang: Accurate Whole-Chip Diagnostic Strategy for Scan Designs with Multiple Faults. J. Electronic Testing 22(2): 151-159 (2006)

Chen-Hsing Wang, Chih-Yen Lo, Min-Sheng Lee, Jen-Chieh Yeh, Chih-Tsun Huang, Cheng-Wen Wu, Shi-Yu Huang: A network security processor design based on an integrated SOC design and test platform. DAC 2006: 490-495

Ying-Chieh Chuang, Shih-Fang Chen, Shi-Yu Huang, Ya-Chin King: Low-cost logarithmic CMOS image sensing by nonlinear analog-to-digital conversion. IEEE Trans. Consumer Electronics 51(4): 1212-1217 (2005)

Yen-Fong Lee, Shi-Yu Huang, Sheng-Yu Hsu, I-Ling Chen, Cheng-Tao Shieh, Jian-Cheng Lin, Shih-Chieh Chang: Power estimation starategies for a low-power security processor. ASP-DAC 2005: 367-371

Jheng-Syun Yang, Shi-Yu Huang: Quick Scan Chain Diagnosis Using Signal Profiling. ICCD 2005: 157-160

Shi-Yu Huang: A Fading Algorithm For Sequential Fault Diagnosis. DFT 2004: 139-147

Shi-Yu Huang: A Symbolic Inject-and-Evaluate Paradigm for Byzantine Fault Diagnosis. J. Electronic Testing 19(2): 161-172 (2003)

Hong-Chou Kao, Ming-Fu Tsai, Shi-Yu Huang, Cheng-Wen Wu, Wen-Feng Chang, Shyue-Kung Lu: Efficient Double Fault Diagnosis for CMOS Logic Circuits With a Specific Application to Generic Bridging Faults. J. Inf. Sci. Eng. 19(4): 571-587 (2003)

Yu-Chiun Lin, Shi-Yu Huang: Chip-Level Diagnostic Strategy for Full-Scan Designs with Multiple Faults. Asian Test Symposium 2003: 38-43

MingHung Lee, TingTing Hwang, Shi-Yu Huang: Decomposition of Extended Finite State Machine for Low Power Design. DATE 2003: 11152-11153

Shyue-Kung Lu, Jian-Long Chen, Cheng-Wen Wu, Ken-Feng Chang, Shi-Yu Huang: Combinational circuit fault diagnosis using logic emulation. ISCAS (5) 2003: 549-552

Shi-Yu Huang: Diagnosis Of Byzantine Open-Segment Faults. Asian Test Symposium 2002: 248-

Horng-Bin Wang, Shi-Yu Huang, Jing-Reng Huang: Gate-Delay Fault Diagnosis Using the Inject-and-Evaluate Paradigm. DFT 2002: 117-128

Shi-Yu Huang: Speeding Up The Byzantine Fault Diagnosis Using Symbolic Simulation. VTS 2002: 193-200

Shi-Yu Huang, Kwang-Ting Cheng, Kuang-Chien Chen: Verifying sequential equivalence using ATPG techniques. ACM Trans. Design Autom. Electr. Syst. 6(2): 244-275 (2001)

Shi-Yu Huang: Towards the logic defect diagnosis for partial-scan designs. ASP-DAC 2001: 313-318

Shi-Yu Huang: On speeding up extended finite state machines using catalyst circuitry. ASP-DAC 2001: 583-588

Chih-Wea Wang, Ruey-Shing Tzeng, Chi-Feng Wu, Chih-Tsun Huang, Cheng-Wen Wu, Shi-Yu Huang, Shyh-Horng Lin, Hsin-Po Wang: A Built-in Self-Test and Self-Diagnosis Scheme for Heterogeneous SRAM Clusters. Asian Test Symposium 2001: 103-

Shi-Yu Huang: On Improving the Accuracy Of Multiple Defect Diagnosis. VTS 2001: 34-41

Shi-Yu Huang, Kwang-Ting Cheng, Kuang-Chien Chen, Chung-Yang Huang, Forrest Brewer: AQUILA: An Equivalence Checking System for Large Sequential Designs. IEEE Trans. Computers 49(5): 443-464 (2000)

Shi-Yu Huang, Sudhakar M. Reddy: High Performance/Delay Testing. Asian Test Symposium 2000: 490-

Shi-Yu Huang, Kwang-Ting Cheng: ErrorTracer: design error diagnosis based on fault simulation techniques. IEEE Trans. on CAD of Integrated Circuits and Systems 18(9): 1341-1352 (1999)

Shi-Yu Huang, Kuang-Chien Chen, Kwang-Ting Cheng: AutoFix: a hybrid tool for automatic logic rectification. IEEE Trans. on CAD of Integrated Circuits and Systems 18(9): 1376-1384 (1999)

Kwang-Ting Cheng, Shi-Yu Huang, Wei-Jin Dai: Fault emulation: A new methodology for fault grading. IEEE Trans. on CAD of Integrated Circuits and Systems 18(10): 1487-1495 (1999)

Yi-Min Jiang, Shi-Yu Huang, Kwang-Ting Cheng, Deborah C. Wang, ChingYen Ho: A Hybrid Power Model for RTL Power Estimation. ASP-DAC 1998: 551-556

Shi-Yu Huang, Kwang-Ting Cheng, Kuang-Chien Chen, Juin-Yeu Joseph Lu: Fault-Simulation Based Design Error Diagnosis for Sequential Circuits. DAC 1998: 632-637

Shi-Yu Huang, Kwang-Ting Cheng, Kuang-Chien Chen: AQUILA: An equivalence verifier for large sequential circuits. ASP-DAC 1997: 455-460

Shi-Yu Huang, Kwang-Ting Cheng, Kuang-Chien Chen, David Ihsin Cheng: Error Tracer: A Fault-Simualtion-Based Approach to Design Error Diagnosis. ITC 1997: 974-981

Shi-Yu Huang, Kuang-Chien Chen, Kwang-Ting Cheng: Incremental logic rectification. VTS 1997: 143-149

Shi-Yu Huang, Kuang-Chien Chen, Kwang-Ting Cheng, Tien-Chien Lee: Compact Vector Generation for Accurate Power Simulation. DAC 1996: 161-164

Shi-Yu Huang, Kuang-Chien Chen, Kwang-Ting Cheng: Error Correction Based on Verification Techniques. DAC 1996: 258-261

Shi-Yu Huang, Kwang-Ting Cheng, Kuang-Chien Chen: On Verifying the Correctness of Retimed Circuits. Great Lakes Symposium on VLSI 1996: 277-

Shi-Yu Huang, Kwang-Ting Cheng, Kuang-Chien Chen, Mike Tien-Chien Lee: A novel methodology for transistor-level power estimation. ISLPED 1996: 67-72

Shi-Yu Huang, Kwang-Ting Cheng, Kuang-Chien Chen, Uwe Gläser: An ATPG-Based Framework for Verifying Sequential Equivalence. ITC 1996: 865-874

Kwang-Ting Cheng, Shi-Yu Huang, Wei-Jin Dai: Fault emulation: a new approach to fault grading. ICCAD 1995: 681-686