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 | 2013 | |
|---|---|---|
| j22 |      | Shih-Hsu Huang, Wen-Pin Tu, Chia-Ming Chang, Song-Bin Pan: Low-power anti-aging zero skew clock gating. ACM Trans. Design Autom. Electr. Syst. 18(2): 27 (2013) |
| c34 | | Wen-Pin Tu, Shih-Hsu Huang, Chun-Hua Cheng: Co-synthesis of data paths and clock control paths for minimum-period clock gating. DATE 2013: 1831-1836 |
| 2012 | ||
| j21 | | Shih-Hsu Huang, Wen-Pin Tu, Bing-Hung Li: High-Level Synthesis for Minimum-Area Low-Power Clock Gating. J. Inf. Sci. Eng. 28(5): 971-988 (2012) |
| c33 | | Chun-Hua Cheng, Wei-Shuo Tzeng, Shih-Hsu Huang: Simultaneous wafer bonding type selection and layer assignment for TSV count minimization. APCCAS 2012: 627-630 |
| c32 | | Wen-Pin Tu, Shih-Hsu Huang, Chun-Hua Cheng: Clock period minimization with minimum area overhead in high-level synthesis of nonzero clock skew circuits. ASP-DAC 2012: 245-250 |
| c31 | | Wen-Pin Tu, Shih-Wei Wu, Shih-Hsu Huang, Mely Chen Chi: NBTI-aware dual threshold voltage assignment for leakage power reduction. ISCAS 2012: 349-352 |
| c30 | | Hua-Hsin Yeh, Shih-Hsu Huang, Chun-Hua Cheng: A formal approach to slack-driven high-level synthesis. ISCAS 2012: 584-587 |
| 2011 | ||
| j20 | | Shih-Hsu Huang, Guan-Yu Jhuo, Wei-Lun Huang: Minimum Inserted Buffers for Clock Period Minimization. J. Inf. Sci. Eng. 27(5): 1513-1526 (2011) |
| j19 | | Chih-Hung Lee, Shih-Hsu Huang, Chun-Hua Cheng: Accurate TSV Number Minimization in High-Level Synthesis. J. Inf. Sci. Eng. 27(5): 1527-1543 (2011) |
| c29 | | Wen-Pin Tu, Yen-Hsin Lee, Shih-Hsu Huang: TSV sharing through multiplexing for TSV count minimization in high-level synthesis. SoCC 2011: 156-159 |
| 2010 | ||
| j18 | | Shih-Hsu Huang, Chun-Hua Cheng: Resource Selection and Binding of Nonzero Clock Skew Circuits for Standby Leakage Current Minimization. J. Inf. Sci. Eng. 26(6): 2249-2266 (2010) |
| c28 | | Shih-Hsu Huang, Chia-Ming Chang, Wen-Pin Tu, Song-Bin Pan: Critical-PMOS-aware clock tree design methodology for anti-aging zero skew clock gating. ASP-DAC 2010: 480-485 |
| 2009 | ||
| j17 | | Shih-Hsu Huang, Chun-Hua Cheng, Song-Bin Pan: Synthesis of Anti-Aging Gated Clock Designs. J. Inf. Sci. Eng. 25(6): 1651-1670 (2009) |
| j16 | | Shih-Hsu Huang, Chun-Hua Cheng, Da-Chen Tzeng: Simultaneous Clock Skew Scheduling and Power-Gated Module Selection for Standby Leakage Minimization. J. Inf. Sci. Eng. 25(6): 1707-1722 (2009) |
| j15 | | Shih-Hsu Huang, Chun-Hua Cheng: Minimum-Period Register Binding. IEEE Trans. on CAD of Integrated Circuits and Systems 28(8): 1265-1269 (2009) |
| j14 | | Shih-Hsu Huang, Chia-Ming Chang, Yow-Tyng Nieh: Opposite-phase register switching for peak current minimization. ACM Trans. Design Autom. Electr. Syst. 14(1) (2009) |
| c27 | | Shih-Hsu Huang, Chun-Hua Cheng: Timing driven power gating in high-level synthesis. ASP-DAC 2009: 173-178 |
| c26 | | Jheng-Fu Yeh, Chun-Hua Cheng, Shih-Hsu Huang: Surge Current Minimization in High-level Synthesis. ISCAS 2009: 1513-1516 |
| 2008 | ||
| j13 | | Shih-Hsu Huang, Chun-Hua Cheng: An ILP Approach to the Simultaneous Application of Operation Scheduling and Power Management. IEICE Transactions 91-A(1): 375-382 (2008) |
| j12 | | Shih-Hsu Huang, Chun-Hua Cheng: Power-Management Scheduling for Peak Power Minimization. J. Inf. Sci. Eng. 24(6): 1647-1668 (2008) |
| c25 | | Chia-Ming Chang, Shih-Hsu Huang, Yuan-Kai Ho, Jia-Zong Lin, Hsin-Po Wang, Yu-Sheng Lu: Type-matching clock tree for zero skew clock gating. DAC 2008: 714-719 |
| 2007 | ||
| j11 | | Yow-Tyng Nieh, Shih-Hsu Huang, Sheng-Yu Hsu: Opposite-Phase Clock Tree for Peak Current Reduction. IEICE Transactions 90-A(12): 2727-2735 (2007) |
| j10 | | Shih-Hsu Huang, Chia-Ming Chang, Yow-Tyng Nieh: A Fast Register Scheduling Approach to the Architecture of Multiple Clocking Domains. J. Inf. Sci. Eng. 23(6): 1681-1705 (2007) |
| j9 | | Shih-Hsu Huang, Yow-Tyng Nieh: Clock skew scheduling with race conditions considered. ACM Trans. Design Autom. Electr. Syst. 12(4) (2007) |
| c24 | | Shih-Hsu Huang, Chun-Hua Cheng, Chia-Ming Chang, Yow-Tyng Nieh: Clock Period Minimization with Minimum Delay Insertion. DAC 2007: 970-975 |
| c23 | | Shih-Hsu Huang, Chu-Liao Wang, Man-Lin Huang: A Floorplan-Based Power Network Analysis Methodology for System-on-Chip Designs. EUC 2007: 507-516 |
| c22 | | Wei-Ting Yen, Shih-Hsu Huang, Chun-Hua Cheng: Simultaneous Operation Scheduling and Operation Delay Selection to Minimize Cycle-by-Cycle Power Differential. EUC Workshops 2007: 638-647 |
| 2006 | ||
| j8 | | Shih-Hsu Huang, Chun-Hua Cheng: An ILP Approach to the Slack Driven Scheduling Problem. IEICE Transactions 89-A(6): 1852-1858 (2006) |
| j7 | | Shih-Hsu Huang, Yow-Tyng Nieh: Synthesis of nonzero clock skew circuits. IEEE Trans. on CAD of Integrated Circuits and Systems 25(6): 961-976 (2006) |
| c21 | | Shih-Hsu Huang, Chun-Hua Cheng, Chung-Hsin Chiang, Chia-Ming Chang: Peak Power Minimization through Power Management Scheduling. APCCAS 2006: 868-871 |
| c20 | | Shih-Hsu Huang, Chun-Hua Cheng: Operation Scheduling for False Loop Free Circuits. APCCAS 2006: 1619-1622 |
| c19 | | Shih-Hsu Huang, Chia-Ming Chang, Yow-Tyng Nieh: Fast multi-domain clock skew scheduling for peak current reduction. ASP-DAC 2006: 254-259 |
| c18 | | Shih-Hsu Huang, Chun-Hua Cheng, Yow-Tyng Nieh, Wei-Chieh Yu: Register binding for clock period minimization. DAC 2006: 439-444 |
| c17 | | Shih-Hsu Huang, Chia-Ming Chang, Yow-Tyng Nieh: State re-encoding for peak current minimization. ICCAD 2006: 33-38 |
| c16 | | Shih-Hsu Huang, Chun-Hua Cheng, Chung-Hsin Chiang, Chia-Ming Chang: An ILP Approach to the Simultaneous Application of Operation Scheduling and Power Management. JCIS 2006 |
| c15 | | Shih-Hsu Huang, Shi-Zhi Liu, Yi-Rung Chen, Jian-Yuan Lai: High-Speed Fuzzy Inference Processor Using Active Rules Identification. JCIS 2006 |
| 2005 | ||
| j6 | | Shih-Hsu Huang, Chung-Hsin Chiang, Chun-Hua Cheng: Three-dimension scheduling under multi-cycle interconnect communications. IEICE Electronic Express 2(4): 108-114 (2005) |
| j5 | | Shih-Hsu Huang, Jian-Yuan Lai: A High Speed Fuzzy Inference Processor with Dynamic Analysis and Scheduling Capabilities. IEICE Transactions 88-D(10): 2410-2416 (2005) |
| j4 | | Shih-Hsu Huang, Jian-Yuan Lai: High-Speed VLSI Fuzzy Inference Processor for Trapezoid-Shaped Membership Functions. J. Inf. Sci. Eng. 21(3): 607-626 (2005) |
| c14 | | Yow-Tyng Nieh, Shih-Hsu Huang, Sheng-Yu Hsu: Minimizing peak current via opposite-phase clock tree. DAC 2005: 182-185 |
| c13 | | Shih-Hsu Huang, Yow-Tyng Nieh, Feng-Pin Lu: Race-condition-aware clock skew scheduling. DAC 2005: 475-478 |
| c12 | | Shih-Hsu Huang, Yi-Rung Chen: VLSI implementation of type-2 fuzzy inference processor. ISCAS (4) 2005: 3307-3310 |
| c11 | | Shih-Hsu Huang, Chun-Hua Cheng: A formal approach to the slack driven scheduling problem in high-level synthesis. ISCAS (6) 2005: 5633-5636 |
| c10 | | Chih-Hung Lee, Chin-Hung Su, Shih-Hsu Huang, Chih-Yuan Lin, Tsai-Ming Hsieh: Floorplanning with clock tree estimation. ISCAS (6) 2005: 6244-6247 |
| 2004 | ||
| j3 | | Shih-Hsu Huang, Yi-Siang Hsu, Chiu-Cheng Lin: A Timing Driven Crosstalk Optimizer for Gridded Channel Routing. IEICE Transactions 87-D(6): 1575-1581 (2004) |
| 2003 | ||
| c9 | | Shih-Hsu Huang, Yow-Tyng Nieh: Clock Period Minimization of Non-Zero Clock Skew Circuits. ICCAD 2003: 809-812 |
| 2002 | ||
| c8 | | Shih-Hsu Huang, Wen-Hon Peng, Jian-Yuan Lai: Automatic synthesis of fuzzy systems based on trapezoid-shaped membership functions. APCCAS (2) 2002: 43-46 |
| c7 | | Shih-Hsu Huang, Yi-Siang Hsu: A timing driven approach for crosstalk minimization in gridded channel routing. APCCAS (1) 2002: 263-266 |
| c6 | | Shih-Hsu Huang, Chu-Liao Wang: An effective floorplan-based power distribution network design methodology under reliability constraints. ISCAS (1) 2002: 353-356 |
| 2001 | ||
| c5 | | Shih-Hsu Huang, Jian-Yuan Lai: A High Speed VLSI Fuzzy Logic Controller With Pipeline Architecture. FUZZ-IEEE 2001: 1054-1057 |
| c4 | | Shih-Hsu Huang: An effective low power design methodology based on interconnect prediction. SLIP 2001: 189-194 |
| 2000 | ||
| c3 | | Mely Chen Chi, Shih-Hsu Huang: A Reliable Clock Tree Design Methodology for ASIC Designs. ISQED 2000: 269-274 |
| 1995 | ||
| j2 | | Shih-Hsu Huang, Cheng-Tsung Hwang, Yu-Chin Hsu, Yen-Jen Oyang: A new approach to schedule operations across nested-ifs and nested-loops. Microprocessing and Microprogramming 41(1): 37-52 (1995) |
| j1 | | Shih-Hsu Huang, Yu-Chin Hsu, Yen-Jen Oyang: A new scheduling algorithm for synthesizing the control blocks of control-dominated circuits. Microprocessing and Microprogramming 41(7): 501-519 (1995) |
| c2 | | Shih-Hsu Huang, Ta-Yung Liu, Yu-Chin Hsu, Yen-Jen Oyang: Synthesis of false loop free circuits. ASP-DAC 1995 |
| 1992 | ||
| c1 | | Shih-Hsu Huang, Cheng-Tsung Hwang, Yu-Chin Hsu, Yen-Jen Oyang: A new approach to schedule operations across nested-ifs and nested-loops. MICRO 1992: 268-271 |
Colors in the list of coauthors
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