| 2005 | ||
|---|---|---|
| c5 | Tim Fox, Lou Covey, Susan Mack, David Heacock, Ed P. Huijbregts, Vess Johnson, Avner Kornfeld, Andrew Yang, Paul S. Zuchowski: Should our power approach be current? DAC 2005: 611 | |
| 2003 | ||
| c4 | Raymond X. Nijssen, Ed P. Huijbregts: A complete design for power methodology and flow for large ASICs. ISPD 2003: 106-108 | |
| 1994 | ||
| c3 | ||
| c2 | Ed P. Huijbregts, Jos T. J. van Eijndhoven, Jochen A. G. Jess: On Design Rule Correct Maze Routing. EDAC-ETC-EUROASIC 1994: 407-411 | |
| 1993 | ||
| j1 | Ed P. Huijbregts, Jochen A. G. Jess: General gate array routing using a k-terminal net routing algorithm with failure prediction. IEEE Trans. VLSI Syst. 1(4): 473-481 (1993) | |
| c1 | Ed P. Huijbregts, Jochen A. G. Jess: A Multiple Terminal Net Routing Algorithm Using Failure Prediction. VLSI Design 1993: 84-89 | |
| 1 | Lou Covey | |
| 2 | Jos T. J. van Eijndhoven | |
| 3 | Tim Fox | |
| 4 | David Heacock | |
| 5 | Jochen A. G. Jess | |
| 6 | Vess Johnson | |
| 7 | Avner Kornfeld | |
| 8 | Susan Mack | |
| 9 | Raymond X. Nijssen | |
| 10 | Hua Xue | |
| 11 | Andrew Yang | |
| 12 | Paul S. Zuchowski |
Colors in the list of coauthors
Last update Wed May 22 06:33:58 2013 CET by the DBLP Team —
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