Ibrahim Hur

Ferad Zyulkyarov, Srdjan Stipic, Tim Harris, Osman S. Unsal, Adrián Cristal, Ibrahim Hur, Mateo Valero: Profiling and Optimizing Transactional Memory Applications. International Journal of Parallel Programming 40(1): 25-56 (2012)

Azam Seyedi, Adrià Armejach, Adrián Cristal, Osman S. Unsal, Ibrahim Hur, Mateo Valero: Circuit design of a dual-versioning L1 data cache. Integration 45(3): 237-245 (2012)

Oriol Arcas, Nehir Sönmez, Gokhan Sayilar, Satnam Singh, Osman S. Unsal, Adrián Cristal, Ibrahim Hur, Mateo Valero: Resource-bounded multicore emulation using Beefarm. Microprocessors and Microsystems - Embedded Hardware Design 36(8): 620-631 (2012)

J. Rubén Titos Gil, Manuel E. Acacio, José M. García, Tim Harris, Adrián Cristal, Osman S. Unsal, Ibrahim Hur, Mateo Valero: Hardware transactional memory with software-defined conflicts. TACO 8(4): 31 (2012)

Wim Heirman, Souradip Sarkar, Trevor E. Carlson, Ibrahim Hur, Lieven Eeckhout: Power-aware multi-core simulation for early design stage hardware/software co-optimization. PACT 2012: 3-12

Gokcen Kestor, Vasileios Karakostas, Osman S. Unsal, Adrián Cristal, Ibrahim Hur, Mateo Valero: RMS-TM: a comprehensive benchmark suite for transactional memory systems (abstracts only). SIGMETRICS Performance Evaluation Review 39(3): 19 (2011)

Gulay Yalcin, Osman S. Unsal, Adrián Cristal, Ibrahim Hur, Mateo Valero: SymptomTM: Symptom-Based Error Detection and Recovery Using Hardware Transactional Memory. PACT 2011: 199-200

Gokcen Kestor, Roberto Gioiosa, Tim Harris, Osman S. Unsal, Adrián Cristal, Ibrahim Hur, Mateo Valero: STM2: A Parallel STM for High Performance Simultaneous Multithreading Systems. PACT 2011: 221-231

Adrià Armejach, Azam Seyedi, J. Rubén Titos Gil, Ibrahim Hur, Adrián Cristal, Osman S. Unsal, Mateo Valero: Using a Reconfigurable L1 Data Cache for Efficient Version Management in Hardware Transactional Memory. PACT 2011: 361-371

Nehir Sönmez, Oriol Arcas, Gokhan Sayilar, Osman S. Unsal, Adrián Cristal, Ibrahim Hur, Satnam Singh, Mateo Valero: From Plasma to BeeFarm: Design Experience of an FPGA-Based Multicore Prototype. ARC 2011: 350-362

Nehir Sönmez, Oriol Arcas, Otto Pflucker, Osman S. Unsal, Adrián Cristal, Ibrahim Hur, Satnam Singh, Mateo Valero: TMbox: A Flexible and Reconfigurable 16-Core Hybrid Transactional Memory System. FCCM 2011: 146-153

Azam Seyedi, Adrià Armejach, Adrián Cristal, Osman S. Unsal, Ibrahim Hur, Mateo Valero: Circuit design of a dual-versioning L1 data cache for optimistic concurrency. ACM Great Lakes Symposium on VLSI 2011: 325-330

Gokcen Kestor, Vasileios Karakostas, Osman S. Unsal, Adrián Cristal, Ibrahim Hur, Mateo Valero: RMS-TM: a comprehensive benchmark suite for transactional memory systems. ICPE 2011: 335-346

Yehuda Afek, Ulrich Drepper, Pascal Felber, Christof Fetzer, Vincent Gramoli, Michael Hohmuth, Etienne Riviere, Per Stenström, Osman S. Unsal, Walther Maldonado, Derin Harmanci, Patrick Marlier, Stephan Diestelhorst, Martin Pohlack, Adrián Cristal, Ibrahim Hur, Aleksandar Dragojevic, Rachid Guerraoui, Michal Kapalka, Sasa Tomic, Guy Korland, Nir Shavit, Martin Nowack, Torvald Riegel: The Velox Transactional Memory Stack. IEEE Micro 30(5): 76-87 (2010)

Ferad Zyulkyarov, Srdjan Stipic, Tim Harris, Osman S. Unsal, Adrián Cristal, Ibrahim Hur, Mateo Valero: Discovering and understanding performance bottlenecks in transactional applications. PACT 2010: 285-294

Ibrahim Hur, Calvin Lin: Feedback mechanisms for improving probabilistic memory prefetching. HPCA 2009: 443-454

Ibrahim Hur, Calvin Lin: A comprehensive approach to DRAM power management. HPCA 2008: 305-316

Ibrahim Hur, Calvin Lin: Memory scheduling for modern microprocessors. ACM Trans. Comput. Syst. 25(4) (2007)

Ibrahim Hur, Calvin Lin: Adaptive History-Based Memory Schedulers for Modern Processors. IEEE Micro 26(1): 22-29 (2006)

Ibrahim Hur, Calvin Lin: Memory Prefetching Using Adaptive Stream Detection. MICRO 2006: 397-408

Ibrahim Hur, Calvin Lin: Adaptive History-Based Memory Schedulers. MICRO 2004: 343-354