Michael Hutton

Mike Hutton, Vaughn Betz: FPGA Synthesis and Physical Design. Embedded Systems Design and Verification 2009: 17

André DeHon, Mike Hutton: Guest Editorial: TRETS Special Edition on the 15th International Symposium on FPGAs. TRETS 1(1) (2008)

Yan Lin, Lei He, Mike Hutton: Stochastic Physical Synthesis Considering Prerouting Interconnect Uncertainty and Process Variation for FPGAs. IEEE Trans. VLSI Syst. 16(2): 124-133 (2008)

Mike Hutton, Paul Chow (Eds.): Proceedings of the ACM/SIGDA 16th International Symposium on Field Programmable Gate Arrays, FPGA 2008, Monterey, California, USA, February 24-26, 2008. ACM 2008, isbn 978-1-59593-934-0

Yan Lin, Mike Hutton, Lei He: Statistical placement for FPGAs considering. IET Computers & Digital Techniques 1(4): 267-275 (2007)

Shuo Zhou, Bo Yao, Hongyu Chen, Yi Zhu, Michael Hutton, Truman Collins, Sridhar Srinivasan, Nan-Chi Chou, Peter Suaris, Chung-Kuan Cheng: Efficient Timing Analysis With Known False Paths Using Biclique Covering. IEEE Trans. on CAD of Integrated Circuits and Systems 26(5): 959-969 (2007)

Paul Chow, Mike Hutton: Integrating FPGAs in high-performance computing: introduction. FPGA 2007: 131

Joachim Pistorius, Mike Hutton, Jay Schleicher, Mihail Iotov, Enoch Julias, Kumara Tharmalingam: Equivalence Verification of FPGA and Structured ASIC Implementations. FPL 2007: 423-428

Dwayne Burns, Ciaran Toal, Kieran McLaughlin, Sakir Sezer, Mike Hutton, Kevin Cackovic: An FPGA Based Memory Efficient Shared Buffer Implementation. FPL 2007: 661-664

Lei Cheng, Deming Chen, Martin D. F. Wong, Mike Hutton, Jason Govig: Timing constraint-driven technology mapping for FPGAs considering false paths and multi-clock domains. ICCAD 2007: 370-375

Jun Mu, Sakir Sezer, Gareth Douglas, Dwayne Burns, Emi Garcia, Mike Hutton, Kevin Cackovic: Accelerating pattern matching for DPI. SoCC 2007: 83-86

André DeHon, Mike Hutton (Eds.): Proceedings of the ACM/SIGDA 15th International Symposium on Field Programmable Gate Arrays, FPGA 2007, Monterey, California, USA, February 18-20, 2007. ACM 2007, isbn 978-1-59593-600-4

Shuo Zhou, Bo Yao, Hongyu Chen, Yi Zhu, Chung-Kuan Cheng, Michael Hutton: Efficient static timing analysis using a unified framework for false paths and multi-cycle paths. ASP-DAC 2006: 73-78

Michael Hutton, Richard Yuan, Jay Schleicher, Gregg Baeckler, Sammy Cheung, Kar Keng Chua, Hee Kong Phoo: A methodology for FPGA to structured-ASIC synthesis and verification. DATE Designers' Forum 2006: 64-69

Lerong Cheng, Jinjun Xiong, Lei He, Mike Hutton: FPGA Performance Optimization Via Chipwise Placement Considering Process Variations. FPL 2006: 1-6

Mike Hutton: FPGA Architecture Design Methodology. FPL 2006: 1

Mike Hutton, Yan Lin, Lei He: Placement and Timing for FPGAs Considering Variations. FPL 2006: 1-7

Shuo Zhou, Yi Zhu, Yuanfang Hu, Ronald L. Graham, Mike Hutton, Chung-Kuan Cheng: Timing model reduction for hierarchical timing analysis. ICCAD 2006: 415-422

Mike Hutton, Joni Dambre (Eds.): The Eigth International Workshop on System-Level Interconnect Prediction (SLIP 2006), Munich, Germany, March 4-5, 2006, Proceedings. ACM 2006, isbn 1-59593-255-0

David M. Lewis, Elias Ahmed, Gregg Baeckler, Vaughn Betz, Mark Bourgeault, David Cashman, David R. Galloway, Mike Hutton, Christopher Lane, Andy Lee, Paul Leventis, Sandy Marquardt, Cameron McClintock, Ketan Padalia, Bruce Pedersen, Giles Powell, Boris Ratchev, Srinivas Reddy, Jay Schleicher, Kevin Stevens, Richard Yuan, Richard Cliff, Jonathan Rose: The Stratix II logic and routing architecture. FPGA 2005: 14-20

Mike Hutton, David Karchmer, Bryan Archell, Jason Govig: Efficient static timing analysis and applications using edge masks. FPGA 2005: 174-183

Boris Ratchev, Mike Hutton, David Mendel: Coping With Uncertainty in FPGA Architecture Design. FPL 2005: 662-665

Shuo Zhou, Bo Yao, Hongyu Chen, Yi Zhu, Chung-Kuan Cheng, Michael Hutton, Truman Collins, Sridhar Srinivasan, Nan-Chi Chou, Peter Suaris: Improving the efficiency of static timing analysis with false paths. ICCAD 2005: 527-531

Lei He, Mike Hutton, Tim Tuan, Steven J. E. Wilton: Challenges and opportunities for low power FPGAs in nanometer technologies. ISLPED 2005: 90

Igor L. Markov, Mike Hutton (Eds.): The Seventh International Workshop on System-Level Interconnect Prediction (SLIP 2005), San Francisco, CA, USA, April 2-3, 2005, Proceedings. ACM 2005, isbn 1-59593-033-7

Michael Hutton, Jay Schleicher, David M. Lewis, Bruce Pedersen, Richard Yuan, Sinan Kaptanoglu, Gregg Baeckler, Boris Ratchev, Ketan Padalia, Mark Bourgeault, Andy Lee, Henry Kim, Rahul Saini: Improving FPGA Performance and Area Using an Adaptive Logic Module. FPL 2004: 135-144

Mike Hutton: Architecture and CAD for FPGAs. SBCCI 2004: 3

Mike Hutton: Advances and trends in FPGA design. SBCCI 2004: 8

Joachim Pistorius, Mike Hutton: Placement rent exponent calculation methods, temporal behaviour and FPGA architecture evaluation. SLIP 2003: 31-38

Michael D. Hutton, Jonathan Rose, Derek G. Corneil: Automatic generation of synthetic sequential benchmark circuits. IEEE Trans. on CAD of Integrated Circuits and Systems 21(8): 928-940 (2002)

Michael Hutton, Vinson Chan, Peter Kazarian, Victor Maruri, Tony Ngai, Jim Park, Rakesh Patel, Bruce Pedersen, Jay Schleicher, Sergey Shumarayev: Interconnect enhancements for a high-speed PLD architecture. FPGA 2002: 3-10

Michael D. Hutton: Interconnect prediction for programmable logic devices. SLIP 2001: 125-131

Michael D. Hutton, Jonathan Rose: Equivalence classes of clone circuits for physical-design benchmarking. ISCAS (6) 1999: 428-431

Michael D. Hutton, Jonathan Rose: Applications of clone circuits to issues in physical-design. ISCAS (6) 1999: 448-451

Michael D. Hutton, Jonathan Rose, Jerry P. Grossman, Derek G. Corneil: Characterization and parameterized generation of synthetic combinational benchmark circuits. IEEE Trans. on CAD of Integrated Circuits and Systems 17(10): 985-996 (1998)

Michael D. Hutton, Jonathan Rose, Derek G. Corneil: Generation of Synthetic Sequential Benchmark Circuits. FPGA 1997: 149-155

Michael D. Hutton, Anna Lubiw: Upward Planning of Single-Source Acyclic Digraphs. SIAM J. Comput. 25(2): 291-311 (1996)

Michael D. Hutton, Jerry P. Grossman, Jonathan Rose, Derek G. Corneil: Characterization and Parameterized Random Generation of Digital Circuits. DAC 1996: 94-99

Michael D. Hutton, Anna Lubiw: Upward Planar Drawing of Single Source Acyclic Digraphs. SODA 1991: 203-211