Wei Hwang

Chih-Wei Chang, Po-Tsang Huang, Lei-Chun Chou, Shang-Lin Wu, Shih-Wei Lee, Ching-Te Chuang, Kuan-Neng Chen, Jin-Chern Chiou, Wei Hwang, Yen-Chi Lee, Chung-Hsi Wu, Kuo-Hua Chen, Chi-Tsung Chiu, Ho-Ming Tong: Through-silicon-via-based double-side integrated microsystem for neural sensing applications. ISSCC 2013: 102-103

Po-Tsang Huang, Wei Hwang: Self-Calibrated Energy-Efficient and Reliable Channels for On-Chip Interconnection Networks. J. Electrical and Computer Engineering 2012 (2012)

Ming-Hung Chang, Shang-Yuan Lin, Wei Hwang: A 0.4 V 520 nW 990 μm² Fully Integrated Frequency-Domain Smart Temperature Sensor in 65 nm CMOS. J. Low Power Electronics 8(1): 63-72 (2012)

Dao-Ping Wang, Wei Hwang: A 45 nm 10T Dual-Port SRAM with Shared Bit-Line Scheme for Low Power Operation. J. Low Power Electronics 8(4): 472-484 (2012)

Ming-Hung Chang, Yi-Te Chiu, Wei Hwang: Design and Iso-Area V_min Analysis of 9T Subthreshold SRAM With Bit-Interleaving Scheme in 65-nm CMOS. IEEE Trans. on Circuits and Systems 59-II(7): 429-433 (2012)

Chien-Yu Lu, Ming-Hsien Tu, Hao-I Yang, Ya-Ping Wu, Huan-Shun Huang, Yuh-Jiun Lin, Kuen-Di Lee, Yung-Shin Kao, Ching-Te Chuang, Shyh-Jye Jou, Wei Hwang: A 0.33-V, 500-kHz, 3.94-$\mu\hbox{W}$ 40-nm 72-Kb 9T Subthreshold SRAM With Ripple Bit-Line Structure and Negative Bit-Line Write-Assist. IEEE Trans. on Circuits and Systems 59-II(12): 863-867 (2012)

Wei-Chih Hsieh, Wei Hwang: All Digital Linear Voltage Regulator for Super- to Near-Threshold Operation. IEEE Trans. VLSI Syst. 20(6): 989-1001 (2012)

Hao-I Yang, Yi-Wei Lin, Mao-Chih Hsia, Geng-Cing Lin, Chi-Shin Chang, Yin-Nien Chen, Ching-Te Chuang, Wei Hwang, Shyh-Jye Jou, Nan-Chun Lien, Hung-Yu Li, Kuen-Di Lee, Wei-Chiang Shih, Ya-Ping Wu, Wen-Ta Lee, Chih-Chiang Hsu: High-performance 0.6V VMIN 55nm 1.0Mb 6T SRAM with adaptive BL bleeder. ISCAS 2012: 1831-1834

Po-Jen Yang, Po-Tsang Huang, Wei Hwang: Substrate noise suppression technique for power integrity of TSV 3D integration. ISCAS 2012: 3274-3277

Yi-Wei Lin, Hao-I Yang, Geng-Cing Lin, Chi-Shin Chang, Ching-Te Chuang, Wei Hwang, Chia-Cheng Chen, Willis Shih, Huan-Shun Huang: A 55nm 0.55v 6T SRAM with variation-tolerant dual-tracking word-line under-drive and data-aware write-assist. ISLPED 2012: 79-84

Mei-Wei Chen, Ming-Hung Chang, Yuan-Hua Chu, Wei Hwang: An energy-efficient level converter with high thermal variation immunity for sub-threshold to super-threshold operation. SoCC 2012: 5-10

Yung-Wei Lin, Hao-I Yang, Mao-Chih Hsia, Yi-Wei Lin, Chien-Hen Chen, Ching-Te Chuang, Wei Hwang, Nan-Chun Lien, Kuen-Di Lee, Wei-Chiang Shih, Ya-Ping Wu, Wen-Ta Lee, Chih-Chiang Hsu: A 55nm 0.5V 128Kb cross-point 8T SRAM with data-aware dynamic supply Write-assist. SoCC 2012: 218-223

Tzu-Ting Chiang, Po-Tsang Huang, Ching-Te Chuang, Kuan-Neng Chen, Jin-Chern Chiou, Kuo-Hua Chen, Chi-Tsung Chiu, Ho-Ming Tong, Wei Hwang: On-chip self-calibrated process-temperature sensor for TSV 3D integration. SoCC 2012: 370-375

Po-Tsang Huang, Wei Hwang: Two-Level FIFO Buffer Design for Routers in On-Chip Interconnection Networks. IEICE Transactions 94-A(11): 2412-2424 (2011)

Po-Tsang Huang, Wei Hwang: A 65 nm 0.165 fJ/Bit/Search 256 , ˟, 144 TCAM Macro Design for IPv6 Lookup Tables. J. Solid-State Circuits 46(2): 507-519 (2011)

Hao-I Yang, Wei Hwang, Ching-Te Chuang: Impacts of gate-oxide breakdown on power-gated SRAM. Microelectronics Journal 42(1): 101-112 (2011)

Hao-I Yang, Shyh-Chyi Yang, Wei Hwang, Ching-Te Chuang: Impacts of NBTI/PBTI on Timing Control Circuits and Degradation Tolerant Design in Nanoscale CMOS SRAM. IEEE Trans. on Circuits and Systems 58-I(6): 1239-1251 (2011)

Wei-Chih Hsieh, Wei Hwang: Adaptive Power Control Technique on Power-Gated Circuitries. IEEE Trans. VLSI Syst. 19(7): 1167-1180 (2011)

Hao-I Yang, Wei Hwang, Ching-Te Chuang: Impacts of NBTI/PBTI and Contact Resistance on Power-Gated SRAM With High-kappa Metal-Gate Devices. IEEE Trans. VLSI Syst. 19(7): 1192-1204 (2011)

Ming-Hung Chang, Chung-Ying Hsieh, Mei-Wei Chen, Wei Hwang: Near-/sub-threshold DLL-based clock generator with PVT-aware locking range compensation. ISLPED 2011: 15-20

Ming-Hung Chang, Yi-Te Chiu, Shu-Lin Lai, Wei Hwang: A 1kb 9T subthreshold SRAM with bit-interleaving scheme in 65nm CMOS. ISLPED 2011: 291-296

Wei-Hung Du, Ming-Hung Chang, Hao-Yi Yang, Wei Hwang: An energy-efficient 10T SRAM-based FIFO memory operating in near-/sub-threshold regions. SoCC 2011: 19-23

Po-Tsang Huang, Yung Chang, Wei Hwang: On-demand memory sub-system for multi-core SoCs. SoCC 2011: 122-127

Hao-I Yang, Shih-Chi Yang, Mao-Chih Hsia, Yung-Wei Lin, Yi-Wei Lin, Chien-Hen Chen, Chi-Shin Chang, Geng-Cing Lin, Yin-Nien Chen, Ching-Te Chuang, Wei Hwang, Shyh-Jye Jou, Nan-Chun Lien, Hung-Yu Li, Kuen-Di Lee, Wei-Chiang Shih, Ya-Ping Wu, Wen-Ta Lee, Chih-Chiang Hsu: A high-performance low VMIN 55nm 512Kb disturb-free 8T SRAM with adaptive VVSS control. SoCC 2011: 197-200

Po-Tsang Huang, Xin-Ru Lee, Hsie-Chia Chang, Chen-Yi Lee, Wei Hwang: A Low Power Differential Cascode Voltage Switch with Pass Gate Pulsed Latch for Viterbi Decoder. J. Low Power Electronics 6(4): 551-562 (2010)

Wei-Chih Hsieh, Wei Hwang: Low quiescent current variable output digital controlled voltage regulator. ISCAS 2010: 609-612

Shi-Wen Chen, Ming-Hung Chang, Wei-Chih Hsieh, Wei Hwang: Fully on-chip temperature, process, and voltage sensors. ISCAS 2010: 897-900

Tien-Hung Lin, Po-Tsang Huang, Wei Hwang: Power noise suppression technique using active decoupling capacitor for TSV 3D integration. SoCC 2010: 209-212

Hao-I Yang, Ching-Te Chuang, Wei Hwang: Impacts of NBTI and PBTI on Power-gated SRAM with High-k Metal-gate Devices. ISCAS 2009: 377-380

Yi-Ming Chang, Ming-Hung Chang, Wei Hwang: A 2.1-mW 0.3V-1.0V wide locking range multiphase DLL using self-estimated SAR algorithm. SoCC 2009: 115-118

Po-Tsang Huang, Wei Hwang: An adaptive congestion-aware routing algorithm for mesh network-on-chip platform. SoCC 2009: 375-378

Po-Tsang Huang, Shu-Wei Chang, Wen-Yen Liu, Wei Hwang: "Green" micro-architecture and circuit co-design for ternary content addressable memory. ISCAS 2008: 3322-3325

Li-Pu Chuang, Ming-Hung Chang, Po-Tsang Huang, Chih-Hao Kan, Wei Hwang: A 5.2mW all-digital fast-lock self-calibrated multiphase delay-locked loop. ISCAS 2008: 3342-3345

Po-Tsang Huang, Wei-Li Fang, Yin-Ling Wang, Wei Hwang: Low Power and Reliable Interconnection with Self-Corrected Green Coding Scheme for Network-on-Chip. NOCS 2008: 77-83

Ming-Hung Chang, Li-Pu Chuang, I-Ming Chang, Wei Hwang: A 300-mV 36-muW multiphase dual digital clock output generator with self-calibration. SoCC 2008: 97-100

Mu-Tien Chang, Po-Tsang Huang, Wei Hwang: A robust ultra-low power asynchronous FIFO memory with self-adaptive power control. SoCC 2008: 175-178

Wei-Chih Hsieh, Wei Hwang: In-situ self-aware adaptive power control system with multi-mode power gating network. SoCC 2008: 215-218

Hao-I Yang, Ssu-Yun Lai, Wei Hwang: Low-power floating bitline 8-T SRAM design with write assistant circuits. SoCC 2008: 239-242

Ming-Hung Chang, Zong-Xi Yang, Wei Hwang: A 1.9mW Portable ADPLL-based Frequency Synthesizer for High Speed Clock Generation. ISCAS 2007: 1137-1140

Wei-Chih Hsieh, Wei Hwang: Low Power On-Chip Current Monitoring Medium-Grained Adaptive Voltage Control. ISCAS 2007: 1637-1640

Mu-Tien Chang, Po-Tsang Huang, Wei Hwang: A 65nm low power 2T1D embedded DRAM with leakage current reduction. SoCC 2007: 207-210

Chang-Hsuan Chang, Ming-Hung Chang, Wei Hwang: A flexible two-layer external memory management for H.264/AVC decoder. SoCC 2007: 219-222

Jen-Wei Yang, Po-Tsang Huang, Wei Hwang: On-Chip DC-DC Converter with Frequency Detector for Dynamic Voltage Scaling Technology. APCCAS 2006: 666-669

Po-Tsang Huang, Wei-Keng Chang, Wei Hwang: Low Power Pre-Comparison Scheme for NOR-Type 10T Content Addressable Memory. APCCAS 2006: 1301-1304

Chi-Chen Lai, Wei Hwang: A Low-Power Reconfigurable Mixed-Radix FFT/IFFT Processor. APCCAS 2006: 1931-1934

Tzu-Chiang Chao, Wei Hwang: A 1.7mW all digital phase-locked loop with new gain generator and low power DCO. ISCAS 2006

Chung-Hsien Hua, Chi-Wei Peng, Wei Hwang: A noise-tolerant matchline scheme with XOR-based conditional keeper for energy-efficient TCAM. ISCAS 2006

Po-Tsang Huang, Wei Hwang: 2-level FIFO architecture design for switch fabrics in network-on-chip. ISCAS 2006

Chung-Hsien Hua, Wei Hwang, Chih-Kai Chen: Noise-tolerant XOR-based conditional keeper for high fan-in dynamic circuits. ISCAS (1) 2005: 444-447

Sangjin Hong, Shu-Shin Chin, Suhwan Kim, Wei Hwang: Power Reduction Technique in Coefficient Multiplications Through Multiplier Characterization. VLSI Signal Processing 38(2): 101-113 (2004)

Stephen V. Kosonocky, Azeez J. Bhavnagarwala, Kenneth Chin, George Gristede, Anne-Marie Haen, Wei Hwang, Mark B. Ketchen, Suhwan Kim, Daniel R. Knebel, Kevin W. Warren, Victor V. Zyuban: Low-power circuits and technology for wireless digital systems. IBM Journal of Research and Development 47(2-3): 283-298 (2003)

Rajiv V. Joshi, Wei Hwang, Ching-Te Chuang: SOI for asynchronous dynamic circuits. ACM Great Lakes Symposium on VLSI 2001: 37-42

W. Chen, Wei Hwang, Prabhakar Kudva, George Gristede, Stephen V. Kosonocky, Rajiv V. Joshi: Mixed multi-threshold differential cascode voltage switch (MT-DCVS) circuit styles and strategies for low power VLSI design. ISLPED 2001: 263-266

Rajiv V. Joshi, Wei Hwang, Andreas Kuehlmann: Design Of Provably Correct Storage Arrays. VLSI Design 2001: 196-

George Gristede, Wei Hwang: A comparison of dual-rail pass transistor logic families in 1.5V, 0.18µm CMOS technology for low power applications. ACM Great Lakes Symposium on VLSI 2000: 101-106

Rajiv V. Joshi, Wei Hwang, S. C. Wilson, Ching-Te Chuang: "Cool low power" 1GHz multi-port register file and dynamic latch in 1.8 V, 0.25 mum SOI and bulk technology (poster session). ISLPED 2000: 203-206

Rajiv V. Joshi, Wei Hwang, S. C. Wilson, Ghavam V. Shahidi, Ching-Te Chuang: A Low Power 900 MHz Register File (8 Ports, 32 Words x 64 Bits) in 1.8V, 0.25µm SOI Technology. VLSI Design 2000: 44-49

Rajiv V. Joshi, Wei Hwang: Design Considerations and Implementation of a High Performance Dynamic Register File. VLSI Design 1999: 526-531

W. K. Luk, Yasunao Katayama, Wei Hwang, Matthew R. Wordeman, T. Kirihata, Akashi Satoh, Seiji Munetoh, H. Wong, B. El-Kareh, P. Xiao, Rajiv V. Joshi: Development of a High Bandwidth Merged Logic/DRAM Multimedia Chip. ICCD 1997: 279-285

Wei Hwang, Rajiv V. Joshi, Walter H. Henkels: A Pulse-To-Static Conversion Latch with a Self-Timed Control Circuit. ICCD 1997: 712-717