- CSB - MetaPress - Google - Bing - Yahoo
 | 2012 | |
|---|---|---|
| j17 |      | Ming-Der Shieh, Yin-Tsung Hwang, Hanho Lee, Chirn Chye Boon, Zhiyuan Yan: Implementations of Signal-Processing Algorithms for OFDM Systems. J. Electrical and Computer Engineering 2012 (2012) |
| j16 | | Yin-Tsung Hwang, Jin-Fa Lin, Ming-Hwa Sheu: Low-Power Pulse-Triggered Flip-Flop Design With Conditional Pulse-Enhancement Scheme. IEEE Trans. VLSI Syst. 20(2): 361-366 (2012) |
| j15 | | Yin-Tsung Hwang, Jin-Fa Lin: Low Voltage and Low Power Divide-By-2/3 Counter Design Using Pass Transistor Logic Circuit Technique. IEEE Trans. VLSI Syst. 20(9): 1738-1742 (2012) |
| c25 | | Yin-Tsung Hwang, Yi-Chih Chen, Cheng-Ru Hong, Yu-Ting Pei, Chi-Ho Chang, Jui-Chi Huang: Design and FPGA implementation of a FMCW radar baseband processor. APCCAS 2012: 392-395 |
| c24 | | Jin-Fa Lin, Yin-Tsung Hwang, Ming-Hwa Sheu: Low power 10-transistor full adder design based on degenerate pass transistor logic. ISCAS 2012: 496-499 |
| c23 | | Yin-Tsung Hwang, Tao-Hsing Huang: Efficient TWIN-VQ audio decoder implementation on a configurable processor using instruction extension. ISCAS 2012: 1010-1013 |
| c22 | | Jing-Shiun Lin, Yin-Tsung Hwang, Po-Han Chu, Ming-Der Shieh, Shih-Hao Fang: An efficient QR decomposition design for MIMO systems. ISCAS 2012: 1508-1511 |
| 2011 | ||
| j14 | | Yin-Tsung Hwang, Cheng-Chen Lin, Ruei-Ting Hung: Lossless Hyperspectral Image Compression System-Based on HW/SW Codesign. Embedded Systems Letters 3(1): 20-23 (2011) |
| j13 | | Yin-Tsung Hwang, Wei-Da Chen: Design and implementation of a high-throughput fully parallel complex-valued QR factorisation chips. IET Circuits, Devices & Systems 5(5): 424-432 (2011) |
| j12 | | Cheng-Chen Lin, Yin-Tsung Hwang: Lossless Compression of Hyperspectral Images Using Adaptive Prediction and Backward Search Schemes. J. Inf. Sci. Eng. 27(2): 419-435 (2011) |
| c21 | | Yin-Tsung Hwang, Feng-Ming Chang, Shin-Wen Chen: Low complexity baseband transceiver design for narrow band power line communication. ISCAS 2011: 442-445 |
| 2010 | ||
| j11 | | Jin-Fa Lin, Yin-Tsung Hwang, Ming-Hwa Sheu: A Low Complexity Low Power Signal Transition Detector Design for Self-Timed Circuits. IEICE Transactions 93-A(4): 843-845 (2010) |
| j10 | | Jin-Fa Lin, Yin-Tsung Hwang, Ming-Hwa Sheu: Low Power Pulse Generator Design Using Hybrid Logic. IEICE Transactions 93-A(6): 1266-1268 (2010) |
| j9 | | Jin-Fa Lin, Yin-Tsung Hwang, Ming-Hwa Sheu: A Low Complexity Dual-Mode Pulse-Triggered Flip-Flop Design Based on Unified AND/XNOR Logic. IEICE Transactions 93-A(12): 2755-2757 (2010) |
| c20 | | Cheng-Chen Lin, Yin-Tsung Hwang, Yi-Chen Chang, Jiun-Jiang Chen, Ming-Wei Liu: Lossless Coding of Multiband Images Using Interband Data Correlation and Error Feedback Prediction Scheme. IIH-MSP 2010: 280-283 |
| c19 | | Yin-Tsung Hwang, Wei-Da Chen: MMSE-QR factorization systolic array design for applications in MIMO signal detections. ISCAS 2010: 4181-4184 |
| 2009 | ||
| c18 | | Yin-Tsung Hwang, Hua-Hsin Luo: Automatic IP Interface Synthesis Supporting Multi-layer Communication Protocols in SoC Designs. IAS 2009: 169-172 |
| c17 | | Chia-Peng Chou, Chien-Hsing Wu, Tsung-Hsien Liu, Yin-Tsung Hwang: Space-Frequency-Coded MIMO OFDM Receivers Based on Gaussian Message Passing. ICC 2009: 1-4 |
| 2008 | ||
| j8 | | Jin-Fa Lin, Yin-Tsung Hwang, Ming-Hwa Sheu: Low Complexity Dual-Mode Pulse Generator Designs. IEICE Transactions 91-A(7): 1812-1815 (2008) |
| c16 | | Yin-Tsung Hwang, Jun-Yen Chen, Jun-Jieh Chiu: HW/SW Auto-Coupling for Fast IP Integration in SoC Designs. ICESS 2008: 556-563 |
| c15 | | Yin-Tsung Hwang, Wei-Da Chen: A low complexity complex QR factorization design for signal detection in MIMO OFDM systems. ISCAS 2008: 932-935 |
| 2007 | ||
| c14 | | Yin-Tsung Hwang, Jin-Fa Lin, Ming-Hwa Sheu, Chia-Jen Sheu: Low Power Multipliers Using Enhenced Row Bypassing Schemes. SiPS 2007: 136-141 |
| c13 | | Cheng-Chen Lin, Yin-Tsung Hwang, Kwan-Hsun Tseng, Shao-Wen Chen: Wavelet Based Lossless Video Compression Using Motion Compensated Temporal Filtering. SiPS 2007: 686-691 |
| 2006 | ||
| c12 | | Yin-Tsung Hwang, Jin-Fa Lin, Ming-Hwa Sheu, Chia-Jen Sheu: Low Power Multiplier Designs Based on Improved Column Bypassing Schemes. APCCAS 2006: 594-597 |
| c11 | | Jin-Fa Lin, Yin-Tsung Hwang, Ming-Hwa Sheu, Cheng-Che Ho: A high speed and energy efficient full adder design using complementary & level restoring carry logic. ISCAS 2006 |
| c10 | | Yin-Tsung Hwang, Jiun-Yan Chen, Ming-Hwa Sheu: Automatic Generation of Programmable Parallel CRC & Scrambler Designs. SiPS 2006: 286-291 |
| 2005 | ||
| j7 | | Tai-Yi Huang, Chung-Ta King, Youn-Long Steve Lin, Yin-Tsung Hwang: The embedded software consortium of taiwan. ACM Trans. Embedded Comput. Syst. 4(3): 612-632 (2005) |
| j6 | | Chien-Ming Wu, Ming-Der Shieh, Chien-Hsing Wu, Yin-Tsung Hwang, Jun-Hong Chen: VLSI architectural design tradeoffs for sliding-window log-MAP decoders. IEEE Trans. VLSI Syst. 13(4): 439-447 (2005) |
| c9 | | Yin-Tsung Hwang, Chen-Yu Tsai, Cheng-Chen Lin: Block-wise adaptive modulation for OFDM WLAN systems. ISCAS (6) 2005: 6098-6101 |
| 2004 | ||
| j5 | | Chien-Hsing Wu, Chien-Ming Wu, Ming-Der Shieh, Yin-Tsung Hwang: High-Speed, Low-Complexity Systolic Designs of Novel Iterative Division Algorithms in GF(2^m). IEEE Trans. Computers 53(3): 375-380 (2004) |
| c8 |  | Chien-Ming Wu, Ming-Der Shieh, Chien-Hsing Wu, Yin-Tsung Hwang, Jun-Hong Chen, Hsin-Fu Lo: VLSI architecture exploration for sliding-window Log-MAP decoders. ISCAS (2) 2004: 513-516 |
| 2003 | ||
| c7 | | Yin-Tsung Hwang, Kuo-Wei Liao, Chien-Hsing Wu: FPGA realization of an OFDM frame synchronization design for dispersive channels. ISCAS (2) 2003: 256-259 |
| 2002 | ||
| c6 | | Yin-Tsung Hwang, Cheng-Ji Chang, Bor-Liang Chen: A rapid prototyping embedded system platform and its HW/SW communication interface generation and verification. APCCAS (1) 2002: 481-484 |
| c5 | | Chien-Hsing Wu, Chien-Ming Wu, Ming-Der Shieh, Yin-Tsung Hwang: An area-efficient systolic division circuit over GF(2/sup m/) for secure communication. ISCAS (5) 2002: 733-736 |
| 2001 | ||
| c4 | | Chien-Hsing Wu, Chien-Ming Wu, Ming-Der Shieh, Yin-Tsung Hwang: Systolic VLSI realization of a novel iterative division algorithm over GF(2m): a high-speed, low-complexity design. ISCAS (4) 2001: 33-36 |
| c3 | | Yin-Tsung Hwang, Jih-Cheng Han, Jing-Yi Liu: Design and implementation of channel equalizers for block transmission systems. ISCAS (4) 2001: 354-357 |
| 1998 | ||
| j4 | | Yin-Tsung Hwang, Jer-Sho Hwang: Simulated Evolution Based Parallel Code Generation for Programmable DSP Processors. J. Inf. Sci. Eng. 14(1): 139-165 (1998) |
| j3 | | Yin-Tsung Hwang, Yuan-Hung Wang, Jer-Sho Hwang: Rapid Prototyping of Hardware / Software Codesign for Embedded Signal Processing. J. Inf. Sci. Eng. 14(3): 605-632 (1998) |
| c2 | | Yin-Tsung Hwang, Yuan-Hung Wang: Communication and Interface Synthesis on a Rapid Prototyping Hardware/Software Codesign System. ISSS 1998: 76-82 |
| 1996 | ||
| c1 | | Ching-Long Su, Yin-Tsung Hwang: Distributed arithmetic-based architectures for high speed IIR filter design. ICPADS 1996: 156-161 |
| 1995 | ||
| j2 | | Yin-Tsung Hwang, Yu Hen Hu: A unified partitioning and scheduling scheme for mapping multi-stage regular iterative algorithms onto processor arrays. VLSI Signal Processing 11(1-2): 133-150 (1995) |
| 1992 | ||
| j1 | | Yin-Tsung Hwang, Yu Hen Hu: MSSM - A design aid for multi-stage systolic mapping. VLSI Signal Processing 4(2-3): 125-145 (1992) |
Colors in the list of coauthors
Last update Wed May 22 13:12:31 2013 CET by the DBLP Team —
Data released under the ODC-BY 1.0 license — See also our legal information page