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M. Incarnati
2010 – today
- 2013
[c2]G. Naso, L. Botticchio, M. Castelli, C. Cerafogli, M. Cichocki, P. Conenna, A. D'Alessandro, L. De Santis, D. Di Cicco, W. Di Francesco, M. L. Gallese, G. Gallo, M. Incarnati, C. Lattaro, A. Macerola, G. G. Marotta, V. Moschiano, D. Orlandi, F. Paolini, S. Perugini, L. Pilolli, P. Pistilli, G. Rizzo, F. Rori, Massimo Rossini, G. Santin, E. Sirizotti, A. Smaniotto, U. Siciliani, M. Tiburzi, R. Meyer, A. Goda, B. Filipiak, Tommaso Vali, M. Helm, R. Ghodsi: A 128Gb 3b/cell NAND flash design using 20nm planar-cell technology. ISSCC 2013: 218-219- 2010
- [c1]G. G. Marotta, A. Macerola, A. D'Alessandro, A. Torsi, C. Cerafogli, C. Lattaro, C. Musilli, D. Rivers, E. Sirizotti, F. Paolini, G. Imondi, G. Naso, G. Santin, L. Botticchio, L. De Santis, L. Pilolli, M. L. Gallese, M. Incarnati, M. Tiburzi, P. Conenna, S. Perugini, V. Moschiano, W. Di Francesco, Matt Goldman, Chris Haid, D. Di Cicco, D. Orlandi, F. Rori, Massimo Rossini, Tommaso Vali, R. Ghodsi, F. Roohparvar: A 3bit/cell 32Gb NAND flash memory at 34nm with 6MB/s program throughput and with dynamic 2b/cell blocks configuration mode for a program throughput increase up to 13MB/s. ISSCC 2010: 444-445
Coauthor Index
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last updated on 2013-04-10 22:27 CEST by the dblp team