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Koji Inoue
2010 – today
- 2013
[c36]Koji Inoue: SMYLE Project: Toward high-performance, low-power computing on manycore-processor SoCs. ASP-DAC 2013: 558-560- [c35]Keitarou Oka, Hiroshi Sasaki, Koji Inoue: Line sharing cache: Exploring cache capacity with frequent line value locality. ASP-DAC 2013: 669-674
- 2012
- [j16]Kenjiro Sugimoto, Koji Inoue, Yoshimitsu Kuroki, Sei-ichiro Kamata: A Linear Manifold Color Descriptor for Medicine Package Recognition. IEICE Transactions 95-D(5): 1264-1271 (2012)
- [j15]Hamid Noori, Farhad Mehdipour, Koji Inoue, Kazuaki Murakami: Improving performance and energy efficiency of embedded processors via post-fabrication instruction set customization. The Journal of Supercomputing 60(2): 196-222 (2012)
- [c34]Hiroshi Sasaki, Teruo Tanimoto, Koji Inoue, Hiroshi Nakamura: Scalability-based manycore partitioning. PACT 2012: 107-116
- [c33]Farhad Mehdipour, Krishna Chaitanya Nunna, Koji Inoue, Kazuaki Murakami: A Three-Dimensional Integrated Accelerator. DSD 2012: 148-151
- [c32]Koji Inoue, Hironobu Saito, Yoshimitsu Kuroki: Local intensity compensation using sparse representation. ICPR 2012: 951-954
- 2011
- [j14]Hideki Miwa, Ryutaro Susukita, Hidetomo Shibamura, Tomoya Hirao, Jun Maki, Makoto Yoshida, Takayuki Kando, Yuichiro Ajima, Ikuo Miyoshi, Toshiyuki Shimizu, Yuji Oinaga, Hisashige Ando, Yuichi Inadomi, Koji Inoue, Mutsumi Aoyagi, Kazuaki Murakami: NSIM: An Interconnection Network Simulator for Extreme-Scale Parallel Computers. IEICE Transactions 94-D(12): 2298-2308 (2011)
- [j13]Farhad Mehdipour, Hiroaki Honda, Koji Inoue, Hiroshi Kataoka, Kazuaki Murakami: A design scheme for a reconfigurable accelerator implemented by single-flux quantum circuits. Journal of Systems Architecture - Embedded Systems Design 57(1): 169-179 (2011)
- [c31]Takaaki Hanada, Hiroshi Sasaki, Koji Inoue, Kazuaki Murakami: Performance evaluation of 3D stacked multi-core processors with temperature consideration. 3DIC 2011: 1-5
- [c30]Farhad Mehdipour, Krishna Chaitanya Nunna, Lovic Gauthier, Koji Inoue, Kazuaki Murakami: A thermal-aware mapping algorithm for reducing peak temperature of an accelerator deployed in a 3D stack. 3DIC 2011: 1-4
- [c29]Farhad Mehdipour, Hiroaki Honda, Hiroshi Kataoka, Koji Inoue, Kazuaki Murakami: Routing architecture and algorithms for a superconductivity circuits-based computing hardware. CCECE 2011: 977-980
- [c28]Koji Inoue, Yoshimitsu Kuroki: Illumination-robust face recognition via sparse representation. VCIP 2011: 1-4
- [e1]Naehyuck Chang, Hiroshi Nakamura, Koji Inoue, Kenichi Osada, Massimo Poncino (Eds.): Proceedings of the 2011 International Symposium on Low Power Electronics and Design, 2011, Fukuoka, Japan, August 1-3, 2011. IEEE/ACM 2011, ISBN 978-1-61284-660-6
- 2010
- [c27]Farhad Mehdipour, Hiroaki Honda, Hiroshi Kataoka, Koji Inoue, Irina Kataeva, Kazuaki Murakami, Hiroyuki Akaike, Akira Fujimaki: Mapping scientific applications on a large-scale data-path accelerator implemented by single-flux quantum (SFQ) circuits. DATE 2010: 993-996
2000 – 2009
- 2009
- [j12]Takatsugu Ono, Koji Inoue, Kazuaki Murakami, Kenji Yoshida: Reducing On-Chip DRAM Energy via Data Transfer Size Optimization. IEICE Transactions 92-C(4): 433-443 (2009)
- [j11]Farhad Mehdipour, Hamid Noori, Koji Inoue, Kazuaki Murakami: Rapid Design Space Exploration of a Reconfigurable Instruction-Set Processor. IEICE Transactions 92-A(12): 3182-3192 (2009)
- [c26]Farhad Mehdipour, Hamid Noori, Bahman Javadi, Hiroaki Honda, Koji Inoue, Kazuaki Murakami: A combined analytical and simulation-based model for performance evaluation of a reconfigurable instruction set processor. ASP-DAC 2009: 564-569
- 2008
- [j10]Naofumi Takagi, Kazuaki Murakami, Akira Fujimaki, Nobuyuki Yoshikawa, Koji Inoue, Hiroaki Honda: Proposal of a Desk-Side Supercomputer with Reconfigurable Data-Paths Using Rapid Single-Flux-Quantum Circuits. IEICE Transactions 91-C(3): 350-355 (2008)
- [j9]Hamid Noori, Maziar Goudarzi, Koji Inoue, Kazuaki Murakami: Temperature-Aware Configurable Cache to Reduce Energy in Embedded Systems. IEICE Transactions 91-C(4): 418-431 (2008)
- [j8]Hamid Noori, Farhad Mehdipour, Koji Inoue, Kazuaki Murakami: A Reconfigurable Functional Unit with Conditional Execution for Multi-Exit Custom Instructions. IEICE Transactions 91-C(4): 497-508 (2008)
- [j7]Hamid Noori, Farhad Mehdipour, Kazuaki Murakami, Koji Inoue, Morteza Saheb Zamani: An architecture framework for an adaptive extensible processor. The Journal of Supercomputing 45(3): 313-340 (2008)
- [c25]Farhad Mehdipour, Hamid Noori, Morteza Saheb Zamani, Koji Inoue, Kazuaki Murakami: Design space exploration for a coarse grain accelerator. ASP-DAC 2008: 685-690
- [c24]Junpei Zushi, Gang Zeng, Hiroyuki Tomiyama, Hiroaki Takada, Koji Inoue: Improved Policies for Drowsy Caches in Embedded Processors. DELTA 2008: 362-367
- [c23]Hamid Noori, Farhad Mehdipour, Koji Inoue, Kazuaki Murakami: Enhancing energy efficiency of processor-based embedded systems through post-fabrication ISA extension. ISLPED 2008: 241-246
- [c22]Hamid Noori, Maziar Goudarzi, Koji Inoue, Kazuaki Murakami: Improving Energy Efficiency of Configurable Caches via Temperature-Aware Configuration Selection. ISVLSI 2008: 363-368
- [c21]Ryutaro Susukita, Hisashige Ando, Mutsumi Aoyagi, Hiroaki Honda, Yuichi Inadomi, Koji Inoue, Shigeru Ishizuki, Yasunori Kimura, Hidemi Komatsu, Motoyoshi Kurokawa, Kazuaki Murakami, Hidetomo Shibamura, Shuji Yamamura, Yunqing Yu: Performance prediction of large-scale parallell system and application using macro-level simulation. SC 2008: 20
- 2007
- [j6]Mariko Sakamoto, Akira Katsuno, Go Sugizaki, Toshio Yoshida, Aiichiro Inoue, Koji Inoue, Kazuaki Murakami: A Next-Generation Enterprise Server System with Advanced Cache Coherence Chips. IEICE Transactions 90-C(10): 1972-1982 (2007)
- [j5]Farhad Mehdipour, Hamid Noori, Morteza Saheb Zamani, Koji Inoue, Kazuaki Murakami: Improving Performance and Energy Saving in a Reconfigurable Processor via Accelerating Control Data Flow Graphs. IEICE Transactions 90-D(12): 1956-1966 (2007)
- [c20]Hamid Noori, Maziar Goudarzi, Koji Inoue, Kazuaki Murakami: The Effect of Nanometer-Scale Technologies on the Cache Size Selection for Low Energy Embedded Systems. ESA 2007: 169-176
- [c19]Hamid Noori, Farhad Mehdipour, Kazuaki Murakami, Koji Inoue, Maziar Goudarzi: Interactive presentation: Generating and executing multi-exit custom instructions for an adaptive extensible processor. DATE 2007: 325-330
- [c18]Hamid Noori, Maziar Goudarzi, Koji Inoue, Kazuaki Murakami: The effect of temperature on cache size tuning for low energy embedded systems. ACM Great Lakes Symposium on VLSI 2007: 453-456
- [c17]Hamid Noori, Farhad Mehdipour, Morteza Saheb Zamani, Koji Inoue, Kazuaki Murakami: Handling Control Data Flow Graphs for a Tightly Coupled Reconfigurable Accelerator. ICESS 2007: 249-260
- [i1]Toshiya Takami, Jun Maki, Jun-ichi Ooba, Yuichi Inadomi, Hiroaki Honda, Ryutaro Susukita, Koji Inoue, Taizo Kobayashi, Rie Nogita, Mutsumi Aoyagi: Multi-physics Extension of OpenFMO Framework. CoRR abs/0707.2630 (2007)
- 2006
- [j4]Koji Inoue: Return Address Protection on Cache Memories. IEICE Transactions 89-C(12): 1937-1947 (2006)
- [c16]Farhad Mehdipour, Hamid Noori, Morteza Saheb Zamani, Kazuaki Murakami, Mehdi Sedighi, Koji Inoue: An Integrated Temporal Partitioning and Mapping Framework for Handling Custom Instructions on a Reconfigurable Functional Unit. Asia-Pacific Computer Systems Architecture Conference 2006: 219-230
- [c15]Farhad Mehdipour, Hamid Noori, Morteza Saheb Zamani, Kazuaki Murakami, Koji Inoue, Mehdi Sedighi: Custom Instruction Generation Using Temporal Partitioning Techniques for a Reconfigurable Functional Unit. EUC 2006: 722-731
- [c14]Hamid Noori, Farhad Mehdipour, Kazuaki Murakami, Koji Inoue, Morteza Saheb Zamani: A Reconfigurable Functional Unit for an Adaptive Dynamic Extensible Processor. FPL 2006: 1-4
- 2005
- [j3]Reiko Komiya, Koji Inoue, Vasily G. Moshnyaga, Kazuaki Murakami: Quantitative Evaluation of State-Preserving Leakage Reduction Algorithm for L1 Data Caches. IEICE Transactions 88-A(4): 862-868 (2005)
- [j2]Hidekazu Tanaka, Koji Inoue: Adaptive Mode Control for Low-Power Caches Based on Way-Prediction Accuracy. IEICE Transactions 88-A(12): 3274-3281 (2005)
- [j1]Koji Inoue: Energy-security tradeoff in a secure cache architecture against buffer overflow attacks. SIGARCH Computer Architecture News 33(1): 81-89 (2005)
- [c13]Shigeharu Matsusaka, Koji Inoue: A Cost Effective Spacial Redundancy with Data-Path Partitioning. ICITA (2) 2005: 51-56
- 2003
- [c12]Hiroshi Takamura, Koji Inoue, Vasily G. Moshnyaga: Reducing Access Count to Register-Files through Operand Reuse. Asia-Pacific Computer Systems Architecture Conference 2003: 112-121
- 2002
- [c11]Koji Inoue, Vasily G. Moshnyaga, Kazuaki Murakami: Reducing power consumption of instruction ROMs by exploiting instruction frequency. APCCAS (2) 2002: 1-6
- [c10]Jun-ni Ohban, Vasily G. Moshnyaga, Koji Inoue: Multiplier energy reduction through bypassing of partial products. APCCAS (2) 2002: 13-17
- [c9]Koji Inoue, Vasily G. Moshnyaga, Kazuaki Murakami: A Low Energy Set-Associative I-Cache with Extended BTB. ICCD 2002: 187-
- [c8]Vasily G. Moshnyaga, Koji Inoue, Mizuka Fukagawa: Reducing energy consumption of video memory by bit-width compression. ISLPED 2002: 142-147
- [c7]Koji Inoue, Vasily G. Moshnyaga, Kazuaki Murakami: A history-based I-cache for low-energy multimedia applications. ISLPED 2002: 148-153
- [c6]Koji Inoue, Vasily G. Moshnyaga, Kazuaki Murakami: Dynamic Tag-Check Omission: A Low Power Instruction Cache Architecture Exploiting Execution Footprints. PACS 2002: 18-32
- [c5]Hiroshi Takamura, Koji Inoue, Vasily G. Moshnyaga: Register File Energy Reduction by Operand Data Reuse. PATMOS 2002: 278-288
- 2000
- [c4]Koji Inoue, Koji Kai, Kazuaki Murakami: Performance/Energy Efficiency of Variable Line-Size Caches for Intelligent Memory Systems. Intelligent Memory Systems 2000: 169-178
1990 – 1999
- 1999
- [c3]Koji Inoue, Koji Kai, Kazuaki Murakami: Dynamically Variable Line-Size Cache Exploiting High On-Chip Memory Bandwidth of Merged DRAM/Logic LSIs. HPCA 1999: 218-222
- [c2]Koji Inoue, Tohru Ishihara, Kazuaki Murakami: Way-predicting set-associative cache for high performance and low energy consumption. ISLPED 1999: 273-275
- [c1]Koji Hashimoto, Hiroto Tomita, Koji Inoue, Katsuhiko Metsugi, Kazuaki Murakami, Shinjiro Inabata, So Yamada, Nobuaki Miyakawa, Hajime Takashima, Kunihiro Kitamura, Shigeru Obara, Takashi Amisaki, Kazutoshi Tanabe, Umpei Nagashima: MOE: A Special-Purpose Parallel Computer for High-Speed, Large-Scale Molecular Orbital Calculation. SC 1999: 58
Coauthor Index
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last updated on 2013-05-04 21:44 CEST by the dblp team