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 | 2012 | |
|---|---|---|
| j16 |      | Michiko Inoue, Akira Taketani, Tomokazu Yoneda, Hideo Fujiwara: Test Pattern Ordering and Selection for High Quality Test Set under Constraints. IEICE Transactions 95-D(12): 3001-3009 (2012) |
| j15 | | Hyunbean Yi, Tomokazu Yoneda, Michiko Inoue, Yasuo Sato, Seiji Kajihara, Hideo Fujiwara: A Failure Prediction Strategy for Transistor Aging. IEEE Trans. VLSI Syst. 20(11): 1951-1959 (2012) |
| c37 | | Yasuo Sato, Seiji Kajihara, Tomokazu Yoneda, Kazumi Hatayama, Michiko Inoue, Yukiya Miura, Satosni Untake, Takumi Hasegawa, Motoyuki Sato, Kotaro Shimamura: DART: Dependable VLSI test architecture and its implementation. ITC 2012: 1-10 |
| c36 | | Yuta Yamato, Tomokazu Yoneda, Kazumi Hatayama, Michiko Inoue: A fast and accurate per-cell dynamic IR-drop estimation method for at-speed scan test pattern validation. ITC 2012: 1-8 |
| 2011 | ||
| j14 | | Michiko Inoue, Tomokazu Yoneda, Muneo Hasegawa, Hideo Fujiwara: Balanced Secure Scan: Partial Scan Approach for Secret Information Protection. J. Electronic Testing 27(2): 99-108 (2011) |
| c35 | | Tomokazu Yoneda, Makoto Nakao, Michiko Inoue, Yasuo Sato, Hideo Fujiwara: Temperature-Variation-Aware Test Pattern Optimization. European Test Symposium 2011: 214 |
| c34 | | Tomokazu Yoneda, Keigo Hori, Michiko Inoue, Hideo Fujiwara: Faster-than-at-speed test for increased test quality and in-field reliability. ITC 2011: 1-9 |
| 2010 | ||
| c33 | | Hiroshi Iwata, Satoshi Ohtake, Michiko Inoue, Hideo Fujiwara: Bipartite Full Scan Design: A DFT Method for Asynchronous Circuits. Asian Test Symposium 2010: 206-211 |
| c32 | | Tomokazu Yoneda, Michiko Inoue, Akira Taketani, Hideo Fujiwara: Seed Ordering and Selection for High Quality Delay Test. Asian Test Symposium 2010: 313-318 |
| c31 | | Zhiqiang You, Jiedi Huang, Michiko Inoue, Jishun Kuang, Hideo Fujiwara: Capture in Turn Scan for Reduction of Test Data Volume, Test Application Time and Test Power. Asian Test Symposium 2010: 371-374 |
| c30 | | Michiko Inoue, Akira Taketani, Tomokazu Yoneda, Hiroshi Iwata, Hideo Fujiwara: Test pattern selection to optimize delay test quality with a limited size of test set. European Test Symposium 2010: 260 |
| c29 | | Hyunbean Yi, Tomokazu Yoneda, Michiko Inoue, Yasuo Sato, Seiji Kajihara, Hideo Fujiwara: Aging test strategy and adaptive test scheduling for SoC failure prediction. IOLTS 2010: 21-26 |
| c28 | | Tomokazu Yoneda, Michiko Inoue, Yasuo Sato, Hideo Fujiwara: Thermal-uniformity-aware X-filling to reduce temperature-induced delay variation for accurate at-speed testing. VTS 2010: 188-193 |
| 2009 | ||
| c27 | | Michiko Inoue, Tomokazu Yoneda, Muneo Hasegawa, Hideo Fujiwara: Partial Scan Approach for Secret Information Protection. European Test Symposium 2009: 143-148 |
| c26 | | Michiko Inoue, Tsuyoshi Suzuki, Hideo Fujiwara: Brief Announcement: Acceleration by Contention for Shared Memory Mutual Exclusion Algorithms. DISC 2009: 172-173 |
| 2008 | ||
| j13 | | Seiji Kajihara, Michiko Inoue: Special Section on Test and Verification of VLSIs. IEICE Transactions 91-D(3): 640-641 (2008) |
| j12 | | Masato Nakasato, Michiko Inoue, Satoshi Ohtake, Hideo Fujiwara: Design for Testability Method to Avoid Error Masking of Software-Based Self-Test for Processors. IEICE Transactions 91-D(3): 763-770 (2008) |
| 2006 | ||
| j11 | | Zhiqiang You, Tsuyoshi Iwagaki, Michiko Inoue, Hideo Fujiwara: A Low Power Deterministic Test Using Scan Chain Disable Technique. IEICE Transactions 89-D(6): 1931-1939 (2006) |
| j10 | | Virendra Singh, Michiko Inoue, Kewal K. Saluja, Hideo Fujiwara: Instruction-Based Self-Testing of Delay Faults in Pipelined Processors. IEEE Trans. VLSI Syst. 14(11): 1203-1215 (2006) |
| 2005 | ||
| j9 | | Virendra Singh, Michiko Inoue, Kewal K. Saluja, Hideo Fujiwara: Delay Fault Testing of Processor Cores in Functional Mode. IEICE Transactions 88-D(3): 610-618 (2005) |
| j8 | | Zhiqiang You, Ken-ichi Yamaguchi, Michiko Inoue, Jacob Savir, Hideo Fujiwara: Power-Constrained Test Synthesis and Scheduling Algorithms for Non-Scan BIST-able RTL Data Paths. IEICE Transactions 88-D(8): 1940-1947 (2005) |
| c25 | | Yuki Yoshikawa, Satoshi Ohtake, Michiko Inoue, Hideo Fujiwara: Design for Testability Based on Single-Port-Change Delay Testing for Data Paths. Asian Test Symposium 2005: 254-259 |
| c24 | | Kazuko Kambe, Michiko Inoue, Hideo Fujiwara, Tsuyoshi Iwagaki: Efficient Constraint Extraction for Template-Based Processor Self-Test Generation. Asian Test Symposium 2005: 444-449 |
| c23 |  | Virendra Singh, Michiko Inoue, Kewal K. Saluja, Hideo Fujiwara: Testing Superscalar Processors in Functional Mode. FPL 2005: 747-750 |
| c22 | | Virendra Singh, Michiko Inoue, Kewal K. Saluja, Hideo Fujiwara: Instruction-based delay fault self-testing of pipelined processor cores. ISCAS (6) 2005: 5686-5689 |
| 2004 | ||
| c21 | | Zhiqiang You, Ken-ichi Yamaguchi, Michiko Inoue, Jacob Savir, Hideo Fujiwara: Power-Constrained DFT Algorithms for Non-Scan BIST-able RTL Data Paths. Asian Test Symposium 2004: 32-39 |
| c20 | | Kazuko Kambe, Michiko Inoue, Hideo Fujiwara: Efficient Template Generation for Instruction-Based Self-Test of Processor Cores. Asian Test Symposium 2004: 152-157 |
| c19 | | Virendra Singh, Michiko Inoue, Kewal K. Saluja, Hideo Fujiwara: Instruction-Based Delay Fault Self-Testing of Processor Cores. VLSI Design 2004: 933- |
| 2003 | ||
| c18 | | Virendra Singh, Michiko Inoue, Kewal K. Saluja, Hideo Fujiwara: Software-Based Delay Fault Testing of Processor Cores. Asian Test Symposium 2003: 68-71 |
| c17 | | Michiko Inoue, Kazuhiro Suzuki, Hiroyuki Okamoto, Hideo Fujiwara: Test Synthesis for Datapaths Using Datapath-Controller Functions. Asian Test Symposium 2003: 294-299 |
| 2002 | ||
| j7 | | Michiko Inoue, Emil Gizdarski, Hideo Fujiwara: Sequential Circuits with Combinational Test Generation Complexity under Single-Fault Assumption. J. Electronic Testing 18(1): 55-62 (2002) |
| j6 | | Kunihiko Hayashi, Michiko Inoue, Toshimitsu Masuzawa, Hideo Fujiwara: A layout adjustment problem for disjoint rectangles preserving orthogonal order. Systems and Computers in Japan 33(2): 31-42 (2002) |
| j5 | | Takashi Ishimizu, Akihiro Fujiwara, Michiko Inoue, Toshimitsu Masuzawa, Hideo Fujiwara: Parallel algorithms for selection on the BSP and BSP* models. Systems and Computers in Japan 33(12): 97-107 (2002) |
| c16 | | Michiko Inoue, Chikateru Jinno, Hideo Fujiwara: An Extended Class of Sequential Circuits with Combinational Test Generation Complexity. ICCD 2002: 200-205 |
| 2001 | ||
| j4 | | Chikara Ohori, Michiko Inoue, Toshimitsu Masuzawa, Hideo Fujiwara: A causal broadcast protocol for distributed mobile systems. Systems and Computers in Japan 32(3): 65-75 (2001) |
| c15 | | Michiko Inoue, Shinya Umetani, Toshimitsu Masuzawa, Hideo Fujiwara: Adaptive Long-Lived O(k2)-Renaming with O(k2) Steps. DISC 2001: 123-135 |
| 2000 | ||
| c14 | | Michiko Inoue, Emil Gizdarski, Hideo Fujiwara: A class of sequential circuits with combinational test generation complexity under single-fault assumption. Asian Test Symposium 2000: 398-403 |
| c13 | | Akihiro Fujiwara, Michiko Inoue, Toshimitsu Masuzawa: Parallelizability of Some P-Complete Problems. IPDPS Workshops 2000: 116-122 |
| 1999 | ||
| j3 | | Akihiro Fujiwara, Michiko Inoue, Toshimitsu Masuzawa, Hideo Fujiwara: A cost optimal parallel algorithm for weighted distance transforms. Parallel Computing 25(4): 405-416 (1999) |
| c12 | | Satoshi Ohtake, Michiko Inoue, Hideo Fujiwara: A Method of Test Generation for Weakly Testable Data Paths Using Test Knowledge Extracted from RTL Description. Asian Test Symposium 1999: 5-12 |
| c11 | | Akihiro Fujiwara, H. Katsuki, Michiko Inoue, Toshimitsu Masuzawa: Parallel Selection Algorithms with Analysis on Clusters. ISPAN 1999: 388-393 |
| c10 | | Takashi Ishimizu, Akihiro Fujiwara, Michiko Inoue, Toshimitsu Masuzawa, Hideo Fujiwara: Parallel Algorithms for All Nearest Neighbors of Binary Images on the BSP Model. ISPAN 1999: 394-399 |
| 1998 | ||
| j2 | | Michiko Inoue, Hideo Fujiwara: An approach to test synthesis from higher level. Integration 26(1-2): 101-116 (1998) |
| c9 | | Michiko Inoue, Takeshi Higashimura, Kenji Noda, Toshimitsu Masuzawa, Hideo Fujiwara: A High-Level Synthesis Method for Weakly Testable Data Paths. Asian Test Symposium 1998: 40-45 |
| c8 | | Kunihiko Hayashi, Michiko Inoue, Toshimitsu Masuzawa, Hideo Fujiwara: A Layout Adjustment Problem for Disjoint Rectangles Preserving Orthogonal Order. Graph Drawing 1998: 183-197 |
| c7 | | Sen Moriya, Michiko Inoue, Toshimitsu Masuzawa, Hideo Fujiwara: SelfStabilizing WaitFree Clock Synchronization with Bounded Space. OPODIS 1998: 129-144 |
| 1997 | ||
| j1 | | Katsuyuki Takabatake, Michiko Inoue, Toshimitsu Masuzawa, Hideo Fujiwara: Non-scan design for testable data paths using thru operation. Systems and Computers in Japan 28(10): 60-68 (1997) |
| c6 | | Katsuyuki Takabatake, Toshimitsu Masuzawa, Michiko Inoue, Hideo Fujiwara: Non-scan design for testable data paths using thru operation. ASP-DAC 1997: 313-318 |
| c5 | | Akihiro Fujiwara, Michiko Inoue, Toshimitsu Masuzawa, Hideo Fujiwara: A Parallel Algorithm for Weighted Distance Transforms. IPPS 1997: 407-412 |
| c4 | | Michiko Inoue, Sen Moriya, Toshimitsu Masuzawa, Hideo Fujiwara: Optimal Wait-Free Clock Synchronisation Protocol on a Shared-Memory Multi-processor System. WDAG 1997: 290-304 |
| 1996 | ||
| c3 | | Yasuo Sato, Michiko Inoue, Toshimitsu Masuzawa, Hideo Fujiwara: A Snapshot Algorithm for Distributed Mobile Systems. ICDCS 1996: 734-743 |
| 1994 | ||
| c2 | | |
| 1992 | ||
| c1 | | |
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