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 | 2006 | |
|---|---|---|
| c6 |      | Shohei Abe, Yohei Hasegawa, Takao Toi, Takeshi Inuo, Hideharu Amano: An adaptive Viterbi decoder on the dynamically reconfigurable processor. FPT 2006: 285-288 |
| 2004 | ||
| c5 | | Hideharu Amano, Takeshi Inuo, Hirokazu Kami, Taro Fujii, Masayasu Suzuki: Techniques for Virtual Hardware on a Dynamically Reconfigurable Processor - An Approach to Tough Cases. FPL 2004: 464-473 |
| 2001 | ||
| c4 | | Tsukasa Yamauchi, Shogo Nakaya, Takeshi Inuo, Nobuki Kajihara: Arithmetic Operation Oriented Reconfigurable Chip: RHW. FPL 2001: 618-622 |
| 2000 | ||
| c3 | | Tsukasa Yamauchi, Shogo Nakaya, Takeshi Inuo, Nobuki Kajihara: Mapping Algorithms for a Multi-Bit Data Path Processing Reconfigurable Chip RHW. FCCM 2000: 281-282 |
| 1998 | ||
| c2 | | Hidenori Sakanashi, Mehrdad Salami, Masaya Iwata, Shogo Nakaya, Tsukasa Yamauchi, Takeshi Inuo, Nobuki Kajihara, Tetsuya Higuchi: Evolvable Hardware Chip for High Precision Printer Image Compression. AAAI/IAAI 1998: 486-491 |
| c1 | | Isamu Kajitani, Tsutomu Hoshino, Daisuke Nishikawa, Hiroshi Yokoi, Shogo Nakaya, Tsukasa Yamauchi, Takeshi Inuo, Nobuki Kajihara, Masaya Iwata, Didier Keymeulen, Tetsuya Higuchi: A Gate-Level EHW Chip: Implementing GA Operations and Reconfigurable Hardware on a Single LSI. ICES 1998: 1-12 |
Colors in the list of coauthors
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