Takahiro Irita

Masaki Fujigaya, Noriaki Sakamoto, Takao Koike, Takahiro Irita, Kohei Wakahara, Tsugio Matsuyama, Keiji Hasegawa, Toshiharu Saito, Akira Fukuda, Kaname Teranishi, Kazuki Fukuoka, Noriaki Maeda, Koji Nii, Takeshi Kataoka, Toshihiro Hattori: A 28nm High-κ metal-gate single-chip communications processor with 1.5GHz dual-core application processor and LTE/HSPA+-capable baseband processor. ISSCC 2013: 156-157

Kenichi Iwata, Takahiro Irita, Seiji Mochizuki, Hiroshi Ueda, Masakazu Ehama, Motoki Kimura, Jun Takemura, Keiji Matsumoto, Eiji Yamamoto, Tadashi Teranuma, Katsuji Takakubo, Hiromi Watanabe, Shinichi Yoshioka, Toshihiro Hattori: A 342 mW Mobile Application Processor With Full-HD Multi-Standard Video Codec and Tile-Based Address-Translation Circuits. J. Solid-State Circuits 45(1): 59-68 (2010)

Tatsuya Kamei, Tetsuhiro Yamada, Takao Koike, Masayuki Ito, Takahiro Irita, Kenichi Nitta, Toshihiro Hattori, Shinichi Yoshioka: A 65nm dual-mode baseband and multimedia application processor SoC with advanced power and memory management. ASP-DAC 2009: 535-539

Kenichi Iwata, Takahiro Irita, Seiji Mochizuki, Hiroshi Ueda, Masakazu Ehama, Motoki Kimura, Jun Takemura, Keiji Matsumoto, Eiji Yamamoto, Tadashi Teranuma, Katsuji Takakubo, Hiromi Watanabe, Shinichi Yoshioka, Toshihiro Hattori: A 342mW mobile application processor with full-HD multi-standard video codec. ISSCC 2009: 158-159

Tetsuya Yamada, Naohiko Irie, Takanobu Tsunoda, Takahiro Irita, Kenji Kitagawa, Ryohei Yoshida, Keisuke Toyama, Motoaki Satoyama: A Hardware Accelerator for Java^TM Platforms on a 130-nm Embedded Processor Core. IEICE Transactions 90-C(2): 523-530 (2007)

Toshihiro Hattori, Takahiro Irita, Masayuki Ito, Eiji Yamamoto, Hisashi Kato, Go Sado, Tetsuhiro Yamada, Kunihiko Nishiyama, Hiroshi Yagi, Takao Koike, Yoshihiko Tsuchihashi, Motoki Higashida, Hiroyuki Asano, Izumi Hayashibara, Ken Tatezawa, Yasuhisa Shimazaki, Naozumi Morino, Yoshihiko Yasu, Tadashi Hoshi, Yujiro Miyairi, Kazumasa Yanagisawa, Kenji Hirose, Saneaki Tamaki, Shinichi Yoshioka, Toshifumi Ishii, Yusuke Kanno, Hiroyuki Mizuno, Tetsuya Yamada, Naohiko Irie, Reiko Tsuchihashi, Nobuto Arai, Tomohiro Akiyama, Koji Ohno: Hierarchical power distribution and power management scheme for a single chip mobile processor. DAC 2006: 292-295

S. Kamae, Takahiro Irita, A. Tsukimori, S. Tarnaki, Toshihiro Hattori, Shinichi Yoshioka: SH-mobile - low power application processor for cellular [3G cellular phones]. ISCAS (5) 2005: 5349-5352

Takahiro Irita, Takayuki Ogura, Minoru Fujishima, Koichiro Hoh: Microprocessor architecture utilizing redundant-binary operation. Systems and Computers in Japan 30(13): 106-115 (1999)

Teppei Tsujita, Takahiro Irita, Minoru Fujishima, Koichiro Hoh: Self-oscillating chaos generator using CMOS multivibrator. KES (1) 1998: 213-217

Koichiro Hoh, Takahiro Irita, Teppei Tsujita, Minoru Fujishima: Generation of chaos with simple sets of semiconductor devices. KES (3) 1998: 250-259