Shota Ishihara

Zhengfan Xia, Shota Ishihara, Masanori Hariyama, Michitaka Kameyama: Design of High-Performance Asynchronous Pipeline Using Synchronizing Logic Gates. IEICE Transactions 95-C(8): 1434-1443 (2012)

Zhengfan Xia, Shota Ishihara, Masanori Hariyama, Michitaka Kameyama: Dual-rail/single-rail hybrid logic design for high-performance asynchronous circuit. ISCAS 2012: 3017-3020

Shota Ishihara, Ryoto Tsuchiya, Yoshiya Komatsu, Masanori Hariyama, Michitaka Kameyama: Implementation of a Low-Power FPGA Based on Synchronous/Asynchronous Hybrid Architecture. IEICE Transactions 94-C(10): 1669-1679 (2011)

Shota Ishihara, Noriaki Idobata, Yoshihiro Nakatani, Masanori Hariyama: A Switch Block for Multi-Context FPGAs Based on Floating-Gate-MOS Functional Pass-Gates Using Multiple/Binary Valued Hybrid Signals? Multiple-Valued Logic and Soft Computing 17(5-6): 553-580 (2011)

Shota Ishihara, Masanori Hariyama, Michitaka Kameyama: A Low-Power FPGA Based on Autonomous Fine-Grain Power Gating. IEEE Trans. VLSI Syst. 19(8): 1394-1406 (2011)

Yoshiya Komatsu, Shota Ishihara, Masanori Hariyama, Michitaka Kameyama: An implementation of an asychronous FPGA based on LEDR/four-phase-dual-rail hybrid architecture. ASP-DAC 2011: 89-90

Shota Ishihara, Yoshiya Komatsu, Masanori Hariyama, Michitaka Kameyama: An Asynchronous FPGA Based on LEDR/4-Phase-Dual-Rail Hybrid Architecture. IEICE Transactions 93-C(8): 1338-1348 (2010)

Shota Ishihara, Noriaki Idobata, Masanori Hariyama, Michitaka Kameyama: A Switch Block Architecture for Multi-Context FPGAs Based on a Ferroelectric-Capacitor Functional Pass-Gate Using Multiple/Binary Valued Hybrid Signals. IEICE Transactions 93-D(8): 2134-2144 (2010)

Masanori Hariyama, Ryoto Tsuchiya, Shota Ishihara, Michitaka Kameyama: An Field-Programmable VLSI Based on Synchronous/Asynchronous Hybrid Architecture. ERSA 2010: 271-274

Shota Ishihara, Masanori Hariyama, Michitaka Kameyama: A low-power FPGA based on autonomous fine-grain power-gating. ASP-DAC 2009: 119-120

Shota Ishihara, Yoshiya Komatsu, Masanori Hariyama, Michitaka Kameyama: An Asynchronous Field-Programmable VLSI Using LEDR/4-Phase-Dual-Rail Protocol Converters. ERSA 2009: 145-150

Shota Ishihara, Noriaki Idobata, Masanori Hariyama, Michitaka Kameyama: A Fine-Grain SIMD Architecture Based on Flexible Ferroelectric-Capacitor Logic. ERSA 2009: 271-274

Masanori Hariyama, Shota Ishihara, Michitaka Kameyama: Evaluation of a Field-Programmable VLSI Based on an Asynchronous Bit-Serial Architecture. IEICE Transactions 91-C(9): 1419-1426 (2008)

Masanori Hariyama, Shota Ishihara, Noriaki Idobata, Michitaka Kameyama: Non-Volatile Multi-Context FPGAs Using Hybrid Multiple-Valued/Binary Context Switching Signals. ERSA 2008: 309-310