Yuichiro Ishii

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	2012
c3		Koji Nii, Yasumasa Tsukamoto, Yuichiro Ishii, Makoto Yabuuchi, Hidehiro Fujiwara, Kazuyoshi Okamoto: A Test Screening Method for 28 nm HK/MG Single-Port and Dual-Port SRAMs Considering with Dynamic Stability and Read/Write Disturb Issues. ATS 2012: 246-251
c2		Yuichiro Ishii, Yasumasa Tsukamoto, Koji Nii, Hidehiro Fujiwara, Makoto Yabuuchi, Koji Tanaka, Shinji Tanaka, Yasuhisa Shimazaki: A 28nm 360ps-access-time two-port SRAM with a time-sharing scheme to circumvent read disturbs. ISSCC 2012: 236-238
	2011
j2		Yuichiro Ishii, Hidehiro Fujiwara, Shinji Tanaka, Yasumasa Tsukamoto, Koji Nii, Yuji Kihara, K. Yanagisawa: A 28 nm Dual-Port SRAM Macro With Screening Circuitry Against Write-Read Disturb Failure Issues. J. Solid-State Circuits 46(11): 2535-2544 (2011)
c1		Yasumasa Tsukamoto, Takeshi Kida, T. Yamaki, Yuichiro Ishii, Koji Nii, Koji Tanaka, Shinji Tanaka, Yuji Kihara: Dynamic stability in minimum operating voltage Vmin for single-port and dual-port SRAMs. CICC 2011: 1-4
	2007
j1		Kumiko Tanaka-Ishii, Yuichiro Ishii: Multilingual phrase-based concordance generation in real-time. Inf. Retr. 10(3): 275-295 (2007)

Coauthor Index

1	Hidehiro Fujiwara	[c3] [c2] [j2]
2	Takeshi Kida	[c1]
3	Yuji Kihara	[j2] [c1]
4	Koji Nii	[c3] [c2] [j2] [c1]
5	Kazuyoshi Okamoto	[c3]
6	Yasuhisa Shimazaki	[c2]
7	Koji Tanaka	[c2] [c1]
8	Shinji Tanaka	[c2] [j2] [c1]
9	Kumiko Tanaka-Ishii (Kumiko Tanaka)	[j1]
10	Yasumasa Tsukamoto	[c3] [c2] [j2] [c1]
11	Makoto Yabuuchi	[c3] [c2]
12	T. Yamaki	[c1]
13	K. Yanagisawa	[j2]

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