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Yehea I. Ismail
2010 – today
- 2013
[j38]Yehea I. Ismail: Editorial Appointments for the 2013-2014 Term. IEEE Trans. VLSI Syst. 21(3): 393-412 (2013)- 2012
- [c78]Moataz Abdelfattah, Maged Ghoneima, Yehea I. Ismail, Amr Lotfy, Mohamed Abdel-moneum, Nasser A. Kurd, Greg Taylor: Modeling the response of Bang-Bang digital PLLs to phase error perturbations. CICC 2012: 1-4
- [c77]Joseph S. Friedman, Nikhil Rangaraju, Yehea I. Ismail, Bruce W. Wessels: InMnAs magnetoresistive spin-diode logic. ACM Great Lakes Symposium on VLSI 2012: 209-214
- [c76]Sally Safwat, Amr Lotfy, Maged Ghoneima, Yehea I. Ismail: A 5-10GHz low power bang-bang all digital PLL based on programmable digital loop filter. ISCAS 2012: 1371-1374
- [c75]Ezz El-Din O. Hussein, Sally Safwat, Maged Ghoneima, Yehea I. Ismail: A 16Gbps low power self-timed SerDes transceiver for multi-core communication. ISCAS 2012: 1660-1663
- [c74]Khaled Salah, Alaa El Rouby, Hani Ragai, Yehea I. Ismail: A closed form expression for TSV-based on-chip spiral inductor. ISCAS 2012: 2325-2328
- [c73]Moataz Abdelfattah, Maged Ghoneima, Yehea I. Ismail, Amr Lotfy, Mohamed Abdelsalam, Mohamed Abdel-moneum, Nasser A. Kurd, Greg Taylor: A novel digital loop filter architecture for bang-bang ADPLL. SoCC 2012: 45-50
- 2011
- [j37]Kian Haghdad, Mohab Anis, Yehea I. Ismail: Floorplanning for low power IC design considering temperature variations. Microelectronics Journal 42(1): 89-95 (2011)
- [j36]Ahmed Shebaita, Debasish Das, Dusan Petranovic, Yehea I. Ismail: A Novel Moment Based Framework for Accurate and Efficient Static Timing Analysis. IEEE Trans. on CAD of Integrated Circuits and Systems 30(8): 1258-1262 (2011)
- [j35]
- [j34]Debasish Das, Ahmed Shebaita, Hai Zhou, Yehea I. Ismail, Kip Killpack: FA-STAC: An Algorithmic Framework for Fast and Accurate Coupling Aware Static Timing Analysis. IEEE Trans. VLSI Syst. 19(3): 443-456 (2011)
- [c72]Khaled Salah, Hani Ragai, Yehea I. Ismail, Alaa El Rouby: Equivalent lumped element models for various n-port Through Silicon Vias networks. ASP-DAC 2011: 176-183
- [c71]Sally Safwat, Ezz El-Din O. Hussein, Maged Ghoneima, Yehea I. Ismail: A 12Gbps all digital low power SerDes transceiver for on-chip networking. ISCAS 2011: 1419-1422
- [c70]Mina Raymond, Maged Ghoneima, Yehea I. Ismail: A dynamic calibration scheme for on-chip process and temperature variations. ISCAS 2011: 2047-2050
- [c69]Song Liu, Seda Ogrenci Memik, Yehea I. Ismail: A Comprehensive Tapered buffer optimization algorithm for unified design metrics. ISCAS 2011: 2277-2280
- [c68]Khaled Salah, Alaa El Rouby, Hani Ragai, Karim Amin, Yehea I. Ismail: Compact lumped element model for TSV in 3D-ICs. ISCAS 2011: 2321-2324
- [c67]Loai G. Salem, Yehea I. Ismail: Fast hysteretic control of on-chip multi-phase switched-capacitor dc-dc converters. ISCAS 2011: 2561-2564
- 2010
- [j33]Jieyi Long, Ja Chun Ku, Seda Ogrenci Memik, Yehea I. Ismail: SACTA: A Self-Adjusting Clock Tree Architecture for Adapting to Thermal-Induced Delay Variation. IEEE Trans. VLSI Syst. 18(9): 1323-1336 (2010)
- [c66]Ezz El-Din O. Hussein, Yehea I. Ismail: A novel variation insensitive clock distribution methodology. ISCAS 2010: 1743-1746
2000 – 2009
- 2009
- [j32]DiaaEldin Khalil, Muhammad M. Khellah, Nam-Sung Kim, Yehea I. Ismail, Tanay Karnik, Vivek De: SRAM dynamic stability estimation using MPFP and its applications. Microelectronics Journal 40(11): 1523-1530 (2009)
- [j31]Maged Ghoneima, Yehea I. Ismail, Muhammad M. Khellah, Vivek De: SSMCB: Low-Power Variation-Tolerant Source-Synchronous Multicycle Bus. IEEE Trans. on Circuits and Systems 56-I(2): 384-394 (2009)
- [j30]Shizhong Mei, Yehea I. Ismail: Stable Parallelizable Model Order Reduction for Circuits With Frequency-Dependent Elements. IEEE Trans. on Circuits and Systems 56-I(6): 1214-1220 (2009)
- [j29]Maged Ghoneima, Yehea I. Ismail, Muhammad M. Khellah, James Tschanz, Vivek De: Serial-Link Bus: A Low-Power On-Chip Bus Architecture. IEEE Trans. on Circuits and Systems 56-I(9): 2020-2032 (2009)
- [j28]DiaaEldin Khalil, Debjit Sinha, Hai Zhou, Yehea I. Ismail: A Timing-Dependent Power Estimation Framework Considering Coupling. IEEE Trans. VLSI Syst. 17(6): 843-847 (2009)
- 2008
- [j27]Ja Chun Ku, Yehea I. Ismail: Area Optimization for Leakage Reduction and Thermal Stability in Nanometer-Scale Technologies. IEEE Trans. on CAD of Integrated Circuits and Systems 27(2): 241-248 (2008)
- [j26]Ahmed Shebaita, Yehea I. Ismail: Multiple Threshold Voltage Design Scheme for CMOS Tapered Buffers. IEEE Trans. on Circuits and Systems 55-II(1): 21-25 (2008)
- [j25]Maged Ghoneima, Muhammad M. Khellah, James Tschanz, Yibin Ye, Nasser A. Kurd, Javed Barkatullah, Srikanth Nimmagadda, Yehea I. Ismail, Vivek K. De: Skewed Repeater Bus: A Low-Power Scheme for On-Chip Buses. IEEE Trans. on Circuits and Systems 55-I(7): 1904-1910 (2008)
- [j24]D. E. Khalil, Muhammad M. Khellah, Nam-Sung Kim, Yehea I. Ismail, Tanay Karnik, Vivek K. De: Accurate Estimation of SRAM Dynamic Stability. IEEE Trans. VLSI Syst. 16(12): 1639-1647 (2008)
- [c65]DiaaEldin Khalil, Yehea I. Ismail: A global interconnect link design for many-core microprocessors. IFMT 2008: 14
- [c64]
- [c63]Sami Kirolos, Yehia Massoud, Yehea I. Ismail: Power-supply-variation-aware timing analysis of synchronous systems. ISCAS 2008: 2418-2421
- [c62]Sami Kirolos, Yehia Massoud, Yehea I. Ismail: Accurate analytical delay modeling of CMOS clock buffers considering power supply variations. ISCAS 2008: 3394-3397
- [c61]DiaaEldin Khalil, Yehea I. Ismail, Muhammad M. Khellah, Tanay Karnik, Vivek De: Analytical Model for the Propagation Delay of Through Silicon Vias. ISQED 2008: 553-556
- 2007
- [j23]Shizhong Mei, Yehea I. Ismail: An Accurate Low-Iteration Algorithm for Effective Capacitance Computation. Journal of Circuits, Systems, and Computers 16(5): 791-800 (2007)
- [j22]Ja Chun Ku, Yehea I. Ismail: On the Scaling of Temperature-Dependent Effects. IEEE Trans. on CAD of Integrated Circuits and Systems 26(10): 1882-1888 (2007)
- [j21]Ja Chun Ku, Serkan Ozdemir, Gokhan Memik, Yehea I. Ismail: Thermal Management of On-Chip Caches Through Power Density Minimization. IEEE Trans. VLSI Syst. 15(5): 592-604 (2007)
- [j20]Ja Chun Ku, Yehea I. Ismail: Thermal-Aware Methodology for Repeater Insertion in Low-Power VLSI Circuits. IEEE Trans. VLSI Syst. 15(8): 963-970 (2007)
- [j19]Maged Ghoneima, Yehea I. Ismail, Muhammad M. Khellah, Vivek K. De: Variation-Tolerant and Low-Power Source-Synchronous Multicycle On-Chip Interconnect Scheme. VLSI Design 2007 (2007)
- [c60]Debasish Das, Ahmed Shebaita, Yehea I. Ismail, Hai Zhou, Kip Killpack: NostraXtalk: a predictive framework for accurate static timing analysis in udsm vlsi circuits. ACM Great Lakes Symposium on VLSI 2007: 25-30
- [c59]Jieyi Long, Ja Chun Ku, Seda Ogrenci Memik, Yehea I. Ismail: A self-adjusting clock tree architecture to cope with temperature variations. ICCAD 2007: 75-82
- [c58]Ahmed Shebaita, Dusan Petranovic, Yehea I. Ismail: Including inductance in static timing analysis. ICCAD 2007: 686-691
- [c57]Frank Huebbers, Ali Dasdan, Yehea I. Ismail: Multi-layer interconnect performance corners for variation-aware timing analysis. ICCAD 2007: 713-718
- [c56]Ahmed Shebaita, Yehea I. Ismail: Variable Threshold Voltage Design Scheme for CMOS Tapered Buffers. ISCAS 2007: 1385-1388
- [c55]
- [c54]Ja Chun Ku, Yehea I. Ismail: A Compact and Accurate Temperature-Dependent Model for CMOS Circuit Delay. ISCAS 2007: 3736-3739
- [c53]DiaaEldin Khalil, Yehea I. Ismail: Approximate Frequency Response Models for RLC Power Grids. ISCAS 2007: 3784-3787
- [c52]Ja Chun Ku, Yehea I. Ismail: Thermal-aware methodology for repeater insertion in low-power VLSI circuits. ISLPED 2007: 86-91
- [c51]Ke Meng, Frank Huebbers, Russ Joseph, Yehea I. Ismail: Modeling and Characterizing Power Variability in Multicore Architectures. ISPASS 2007: 146-157
- [c50]Serkan Ozdemir, Arindam Mallik, Ja Chun Ku, Gokhan Memik, Yehea I. Ismail: Variable latency caches for nanoscale processor. SC 2007: 20
- 2006
- [j18]Maged Ghoneima, Yehea I. Ismail, Muhammad M. Khellah, James Tschanz, Vivek De: Formal derivation of optimal active shielding for low-power on-chip buses. IEEE Trans. on CAD of Integrated Circuits and Systems 25(5): 821-836 (2006)
- [j17]Masud H. Chowdhury, Yehea I. Ismail: Realistic scalability of noise in dynamic circuits. IEEE Trans. VLSI Syst. 14(6): 637-641 (2006)
- [c49]Ja Chun Ku, Yehea I. Ismail: Area optimization for leakage reduction and thermal stability in nanometer scale technologies. ASP-DAC 2006: 231-236
- [c48]Frank Huebbers, Ali Dasdan, Yehea I. Ismail: Computation of accurate interconnect process parameter values for performance corners under process variations. DAC 2006: 797-800
- [c47]Ja Chun Ku, Serkan Ozdemir, Gokhan Memik, Yehea I. Ismail: Power density minimization for highly-associative caches in embedded processors. ACM Great Lakes Symposium on VLSI 2006: 100-104
- [c46]Ahmed Shebaita, Dusan Petranovic, Yehea I. Ismail: Importance of volume discretization of single and coupled interconnects. ICCAD 2006: 119-126
- [c45]Debjit Sinha, DiaaEldin Khalil, Yehea I. Ismail, Hai Zhou: A timing dependent power estimation framework considering coupling. ICCAD 2006: 401-407
- [c44]Debasish Das, Ahmed Shebaita, Hai Zhou, Yehea I. Ismail, Kip Killpack: FA-STAC: A Framework for Fast and Accurate Static Timing Analysis with Coupling. ICCD 2006
- [c43]Maged Ghoneima, Yehea I. Ismail, Muhammad M. Khellah, Vivek De: Reducing the data switching activity of serialized datastreams. ISCAS 2006
- [c42]
- [c41]Keith A. Bowman, James Tschanz, Muhammad M. Khellah, Maged Ghoneima, Yehea I. Ismail, Vivek De: Time-borrowing multi-cycle on-chip interconnects for delay variation tolerance. ISLPED 2006: 79-84
- [c40]Maged Ghoneima, Yehea I. Ismail, Muhammad M. Khellah, Vivek De: Reducing the Data Switching Activity on Serial Link Buses. ISQED 2006: 425-432
- [e2]Gang Qu, Yehea I. Ismail, Narayanan Vijaykrishnan, Hai Zhou (Eds.): Proceedings of the 16th ACM Great Lakes Symposium on VLSI 2006, Philadelphia, PA, USA, April 30 - May 1, 2006. ACM 2006, ISBN 1-59593-347-6
- 2005
- [j16]Chirayu S. Amin, Masud H. Chowdhury, Yehea I. Ismail: Realizable reduction of interconnect circuits including self and mutual inductances. IEEE Trans. on CAD of Integrated Circuits and Systems 24(2): 271-277 (2005)
- [j15]Maged Ghoneima, Yehea I. Ismail: Optimum positioning of interleaved repeaters in bidirectional buses. IEEE Trans. on CAD of Integrated Circuits and Systems 24(3): 461-469 (2005)
- [j14]Chirayu S. Amin, Florentin Dartu, Yehea I. Ismail: Weibull-based analytical waveform model. IEEE Trans. on CAD of Integrated Circuits and Systems 24(8): 1156-1168 (2005)
- [c39]Chirayu S. Amin, Noel Menezes, Kip Killpack, Florentin Dartu, Umakanta Choudhury, Nagib Hakim, Yehea I. Ismail: Statistical static timing analysis: how simple can we get? DAC 2005: 652-657
- [c38]Chirayu S. Amin, Yehea I. Ismail, Florentin Dartu: Piece-wise approximations of RLCK circuit responses using moment matching. DAC 2005: 927-932
- [c37]Gokhan Memik, Masud H. Chowdhury, Arindam Mallik, Yehea I. Ismail: Engineering Over-Clocking: Reliability-Performance Trade-Offs for High-Performance Register Files. DSN 2005: 770-779
- [c36]Noha H. Mahmoud, Maged Ghoneima, Yehea I. Ismail: Physical limitations on the bit-rate of on-chip interconnects. ACM Great Lakes Symposium on VLSI 2005: 13-19
- [c35]Maged Ghoneima, Yehea I. Ismail, Muhammad M. Khellah, James Tschanz, Vivek De: Serial-link bus: a low-power on-chip bus architecture. ICCAD 2005: 541-546
- [c34]Ahmed M. Shebaita, Chirayu S. Amin, Florentin Dartu, Yehea I. Ismail: Expanding the frequency range of AWE via time shifting. ICCAD 2005: 935-938
- [c33]Muhammad M. Khellah, Maged Ghoneima, James Tschanz, Yibin Ye, Nasser A. Kurd, Javed Barkatullah, Srikanth Nimmagadda, Yehea I. Ismail: A Skewed Repeater Bus Architecture for On-Chip Energy Reduction in Microprocessors. ICCD 2005: 253-257
- [c32]Yehea I. Ismail, Muhammad M. Khellah, Maged Ghoneima, James Tschanz, Yibin Ye, Vivek De: Skewing adjacent line repeaters to reduce the delay and energy dissipation of on-chip buses. ISCAS (1) 2005: 592-595
- [c31]Maged Ghoneima, Yehea I. Ismail: Accurate decoupling of capacitively coupled buses. ISCAS (4) 2005: 4146-4149
- [c30]Ja Chun Ku, Serkan Ozdemir, Gokhan Memik, Yehea I. Ismail: Thermal Management of On-Chip Caches Through Power Density Minimization. MICRO 2005: 283-293
- [e1]
- 2004
- [j13]Yehea I. Ismail, Chirayu S. Amin: Computation of signal-threshold crossing times directly from higher order moments. IEEE Trans. on CAD of Integrated Circuits and Systems 23(8): 1264-1276 (2004)
- [j12]Shizhong Mei, Yehea I. Ismail: Modeling skin and proximity effects with reduced realizable RL circuits. IEEE Trans. VLSI Syst. 12(4): 437-447 (2004)
- [j11]Maged Ghoneima, Yehea I. Ismail: Utilizing the effect of relative delay on energy dissipation in low-power on-chip buses. IEEE Trans. VLSI Syst. 12(12): 1348-1359 (2004)
- [c29]Yehea I. Ismail, Chirayu S. Amin: Computation of signal threshold crossing times directly from higher order moments. ICCAD 2004: 246-253
- [c28]Chirayu S. Amin, Florentin Dartu, Yehea I. Ismail: Modeling unbuffered latches for timing analysis. ICCAD 2004: 254-260
- [c27]Maged Ghoneima, Yehea I. Ismail: Formal derivation of optimal active shielding for low-power on-chip buses. ICCAD 2004: 800-807
- [c26]Maged Ghoneima, Yehea I. Ismail: Low power coupling-based encoding for on-chip buses. ISCAS (2) 2004: 325-328
- [c25]Maged Ghoneima, Yehea I. Ismail: Effect of relative delay on the dissipated energy in coupled interconnects. ISCAS (2) 2004: 525-528
- [c24]Daniel Dai, Yehea I. Ismail, Wei Wang, Hanif M. Ladak: Powder-based fabrication techniques for single-wall carbon nanotube circuits. ISCAS (3) 2004: 701-704
- [c23]Maged Ghoneima, Yehea I. Ismail: Delayed line bus scheme: a low-power bus scheme for coupled on-chip buses. ISLPED 2004: 66-69
- [c22]Masud H. Chowdhury, Yehea I. Ismail: Possible Noise Failure Modes in Static and Dynamic Circuits. IWSOC 2004: 123-126
- [c21]Maged Ghoneima, Yehea I. Ismail: Low-power on-chip bus architecture using dynamic relative delays. SoCC 2004: 233-236
- 2003
- [j10]Yehea I. Ismail, Eby G. Friedman: On the Extraction of On-Chip Inductance. Journal of Circuits, Systems, and Computers 12(1): 31-40 (2003)
- [j9]Yehea I. Ismail: Improved model-order reduction by using spacial information in moments. IEEE Trans. VLSI Syst. 11(5): 900-908 (2003)
- [c20]Chirayu S. Amin, Masud H. Chowdhury, Yehea I. Ismail: Realizable RLCK circuit crunching. DAC 2003: 226-231
- [c19]Shizhong Mei, Chirayu S. Amin, Yehea I. Ismail: Efficient model order reduction including skin effect. DAC 2003: 232-237
- [c18]Maged Ghoneima, Yehea I. Ismail: Optimum positioning of interleaved repeaters In bidirectional buses. DAC 2003: 586-591
- [c17]Chirayu S. Amin, Florentin Dartu, Yehea I. Ismail: Weibull Based Analytical Waveform Model. ICCAD 2003: 161-168
- [c16]Noha H. Mahmoud, Yehea I. Ismail: Accurate rise time and overshoots estimation in RLC interconnects. ISCAS (5) 2003: 477-480
- [c15]Masud H. Chowdhury, Chirayu S. Amin, Yehea I. Ismail, Chandramouli V. Kashyap, Byron Krauter: Realizable reduction of RLC circuits using node elimination. ISCAS (3) 2003: 494-497
- [c14]Shizhong Mei, Yehea I. Ismail: Modeling skin effect with reduced decoupled R-L circuits. ISCAS (4) 2003: 588-591
- [c13]Masud H. Chowdhury, Yehea I. Ismail: Analysis of Coupling Noise in Dynamic Circuit. IWSOC 2003: 320-325
- 2002
- [j8]Yehea I. Ismail, Eby G. Friedman, José Luis Neves: Inductance Effects in RLC Trees. Journal of Circuits, Systems, and Computers 11(3): 305- (2002)
- [j7]Yehea I. Ismail, Eby G. Friedman: DTT: direct truncation of the transfer function - an alternative tomoment matching for tree structured interconnect. IEEE Trans. on CAD of Integrated Circuits and Systems 21(2): 131-144 (2002)
- [j6]Yehea I. Ismail, Byron Krauter: Guest editorial: special issue on on-chip inductance in high-speed integrated circuits. IEEE Trans. VLSI Syst. 10(6): 683-684 (2002)
- [j5]
- [c12]Yehea I. Ismail: Efficient model order reduction via multi-node moment matching. ICCAD 2002: 767-774
- [c11]Masud H. Chowdhury, Yehea I. Ismail, Chandramouli V. Kashyap, Byron Krauter: Performance analysis of deep sub micron VLSI circuits in the presence of self and mutual inductance. ISCAS (4) 2002: 197-200
- [c10]Yehea I. Ismail: Evaluating noise pulses in RC networks due to capacitive coupling. ISCAS (5) 2002: 653-656
- 2001
- [j4]Yehea I. Ismail, Eby G. Friedman, José Luis Neves: Exploiting the on-chip inductance in high-speed clock distribution networks. IEEE Trans. VLSI Syst. 9(6): 963-973 (2001)
- 2000
- [j3]Yehea I. Ismail, Eby G. Friedman, José Luis Neves: Equivalent Elmore delay for RLC trees. IEEE Trans. on CAD of Integrated Circuits and Systems 19(1): 83-97 (2000)
- [j2]Yehea I. Ismail, Eby G. Friedman: Effects of inductance on the propagation delay and repeater insertion in VLSI circuits. IEEE Trans. VLSI Syst. 8(2): 195-206 (2000)
1990 – 1999
- 1999
- [j1]Yehea I. Ismail, Eby G. Friedman, José Luis Neves: Figures of merit to characterize the importance of on-chip inductance. IEEE Trans. VLSI Syst. 7(4): 442-449 (1999)
- [c9]Yehea I. Ismail, Eby G. Friedman, José Luis Neves: Equivalent Elmore Delay for RLC Trees. DAC 1999: 715-720
- [c8]Yehea I. Ismail, Eby G. Friedman: Effects of Inductance on the Propagation Delay and Repeater Insertion in VLSI Circuits. DAC 1999: 721-724
- [c7]Yehea I. Ismail, Eby G. Friedman, José Luis Neves: Inductance Effects in RLC Trees. Great Lakes Symposium on VLSI 1999: 56-59
- [c6]Yehea I. Ismail, Eby G. Friedman, José Luis Neves: Repeater insertion in tree structured inductive interconnect. ICCAD 1999: 420-424
- [c5]Yehea I. Ismail, Eby G. Friedman, José Luis Neves: Signal waveform characterization in RLC trees. ISCAS (6) 1999: 190-193
- [c4]Yehea I. Ismail, Eby G. Friedman: Repeater insertion in RLC lines for minimum propagation delay. ISCAS (6) 1999: 404-407
- 1998
- [c3]Yehea I. Ismail, Eby G. Friedman, José Luis Neves: Figures of Merit to Characterize the Importance of On-Chip Inductance. DAC 1998: 560-565
- [c2]Yehea I. Ismail, Eby G. Friedman, José Luis Neves: Dynamic and Short-Circuit Power of CMOS Gates Driving Lossless Transmission Lines. Great Lakes Symposium on VLSI 1998: 39-44
- [c1]Yehea I. Ismail, Eby G. Friedman, José Luis Neves: Power dissipated by CMOS gates driving lossless transmission lines. ISLPED 1998: 139-142
Coauthor Index
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last updated on 2013-02-26 20:13 CET by the dblp team