Atsushi Iwata

Atsushi Iwata, Yoshitaka Murasaka, Tomoaki Maeda, Takafumi Ohmoto: Background Calibration Techniques for Low-Power and High-Speed Data Conversion. IEICE Transactions 94-C(6): 923-929 (2011)

Yudai Honma, Masaki Aida, Hideyuki Shimonishi, Atsushi Iwata: A New Multi-Path Routing Methodology Based on Logit-Type Probability Assignment. IEICE Transactions 94-B(8): 2282-2291 (2011)

Kazuhiro Shimonomura, Seiji Kameda, Atsushi Iwata, Tetsuya Yagi: Wide-Dynamic-Range APS-Based Silicon Retina With Brightness Constancy. IEEE Transactions on Neural Networks 22(9): 1482-1493 (2011)

Takeshi Yoshida, Yoshihiro Masui, Ryoji Eki, Atsushi Iwata, Masayuki Yoshida, Kazumasa Uematsu: A Neural Recording Amplifier with Low-Frequency Noise Suppression. IEICE Transactions 93-C(6): 849-854 (2010)

Yoshihiro Masui, Takeshi Yoshida, Atsushi Iwata: A 2.0 Vpp Input, 0.5 V Supply Delta Amplifier with A-to-D Conversion. IEICE Transactions 92-C(6): 828-834 (2009)

Hideyuki Shimonishi, Hideya Ochiai, Nobuyuki Enomoto, Atsushi Iwata: Building Hierarchical Switch Network Using OpenFlow. INCoS 2009: 391-394

Takeshi Yoshida, Yoshihiro Masui, Ryoji Eki, Atsushi Iwata, Masayuki Yoshida, Kazumasa Uematsu: A Neural Signal Detection Amplifier with Low-frequency Noise Suppression. ISCAS 2009: 661-664

Nobuyuki Enomoto, Hideyuki Shimonishi, Junichi Higuchi, Takashi Yoshikawa, Atsushi Iwata: High-Speed, Short-Latency Multipath Ethernet for Data Center Area Communications. GLOBECOM 2008: 1550-1555

Nobuyuki Enomoto, Hideyuki Shimonishi, Junichi Higuchi, Takashi Yoshikawa, Atsushi Iwata: High-Speed, Short-Latency Multipath Ethernet Transport for Interconnections. Hot Interconnects 2008: 75-84

Hideyuki Shimonishi, Takashi Yoshikawa, Atsushi Iwata: Off-the-path flow handling mechanism forhigh-speed and programmable traffic management. PRESTO 2008: 15-20

Daisuke Kosaka, Makoto Nagata, Yoshitaka Murasaka, Atsushi Iwata: Evaluation of Isolation Structures against High-Frequency Substrate Coupling in Analog/Mixed-Signal Integrated Circuits. IEICE Transactions 90-A(2): 380-387 (2007)

Atsushi Iwata, Takeshi Yoshida, Mamoru Sasaki: Low-Voltage and Low-Noise CMOS Analog Circuits Using Scaled Devices. IEICE Transactions 90-C(6): 1149-1155 (2007)

Daisuke Kosaka, Makoto Nagata, Yoshitaka Murasaka, Atsushi Iwata: Chip-Level Substrate Coupling Analysis with Reference Structures for Verification. IEICE Transactions 90-A(12): 2651-2660 (2007)

Nobuharu Kami, Jun Suzuki, Yoichi Hidaka, Takashi Yoshikawa, Atsushi Iwata: Multilayer In-service Reconfiguration for Network Computing Systems. NCA 2007: 324-331

Atsushi Iwata: Carrier-Grade Ethernet Technologies for Next Generation Wide Area Ethernet. IEICE Transactions 89-B(3): 651-660 (2006)

Masaki Umayabashi, Yoichi Hidaka, Nobuyuki Enomoto, Daisaku Ogasahara, Kazuo Takagi, Atsushi Iwata, Akira Arutaki: Improving Ethernet Reliability and Stability Using Global Open Ethernet Technology. IEICE Transactions 89-B(3): 675-682 (2006)

Takeshi Yoshida, Yoshihiro Masui, Takayuki Mashimo, Mamoru Sasaki, Atsushi Iwata: A 1 V Low-Noise CMOS Amplifier Using Autozeroing and Chopper Stabilization Technique. IEICE Transactions 89-C(6): 769-774 (2006)

Osamu Nomura, Takashi Morie, Keisuke Korekado, Teppei Nakano, Masakazu Matsugu, Atsushi Iwata: An Image-Filtering LSI Processor Architecture for Face/Object Recognition Using a Sorted Projection-Field Model Based on a Merged/Mixed Analog-Digital Architecture. IEICE Transactions 89-C(6): 781-791 (2006)

Kan'ya Sasaki, Takashi Morie, Atsushi Iwata: A VLSI Spiking Feedback Neural Network with Negative Thresholding and Its Application to Associative Memory. IEICE Transactions 89-C(11): 1637-1644 (2006)

Kan'ya Sasaki, Seiji Kameda, Atsushi Iwata: Stereo Matching Algorithm Using a Weighted Average of Costs Aggregated by Various Window Sizes. ACCV (2) 2006: 771-780

Jun Suzuki, Yoichi Hidaka, Junichi Higuchi, Takashi Yoshikawa, Atsushi Iwata: ExpressEther - Ethernet-Based Virtualization Technology for Reconfigurable Hardware Platform. Hot Interconnects 2006: 45-51

Mitsuru Shiozaki, Toru Mukai, Masahiro Ono, Mamoru Sasaki, Atsushi Iwata: A 2.7 Gcps and 7-Multiplexing CDMA Serial Communication Chip Using Two-Step Synchronization Technique. IEICE Transactions 88-C(6): 1233-1240 (2005)

Osamu Nomura, Takashi Morie, Masakazu Matsugu, Atsushi Iwata: A Convolutional Neural Network VLSI Architecture Using Sorting Model for Reducing Multiply-and-Accumulation Operations. ICNC (3) 2005: 1006-1014

Takeshi Yoshida, Miho Akagi, Mamoru Sasaki, Atsushi Iwata: A 1V supply successive approximation ADC with rail-to-rail input voltage range. ISCAS (1) 2005: 192-195

Norihito Fujita, Yuichi Ishikawa, Atsushi Iwata, Rauf Izmailov: Coarse-grain replica management strategies for dynamic replication of Web contents. Computer Networks 45(1): 19-34 (2004)

Tsutomu Yoshimura, Atsushi Iwata: An analysis of interference in synchronous systems. IEICE Electronic Express 1(15): 465-471 (2004)

Keisuke Korekado, Takashi Morie, Osamu Nomura, Hiroshi Ando, Teppei Nakano, Masakazu Matsugu, Atsushi Iwata: A VLSI convolutional neural network for image recognition using merged/mixed analog-digital architecture. Journal of Intelligent and Fuzzy Systems 15(3-4): 173-179 (2004)

Atsushi Iwata, Yoichi Hidaka, Masaki Umayabashi, Nobuyuki Enomoto, Akira Arutaki: Global open ethernet (GOE) system and its performance evaluation. IEEE Journal on Selected Areas in Communications 22(8): 1432-1442 (2004)

Aleksandar Kolarov, Bhaskar Sengupta, Atsushi Iwata: Design of multiple reverse spanning trees in next generation of Ethernet-VPNs. GLOBECOM 2004: 1390-1395

Osamu Nomura, Takashi Morie, Keisuke Korekado, Masakazu Matsugu, Atsushi Iwata: A Convolutional Neural Network VLSI Architecture Using Thresholding and Weight Decomposition. KES 2004: 995-1001

Keisuke Korekado, Takashi Morie, Osamu Nomura, Hiroshi Ando, Teppei Nakano, Masakazu Matsugu, Atsushi Iwata: A Convolutional Neural Network VLSI for Image Recognition Using Merged/Mixed Analog-Digital Architecture. KES 2003: 169-176

Teppei Nakano, Takashi Morie, Makoto Nagata, Atsushi Iwata: A cellular-automaton-type image extraction algorithm and its implementation using an FPGA. APCCAS (2) 2002: 197-200

Norihito Fujita, Nobuyuki Enomoto, Atsushi Iwata, Rauf Izmailov: Coarse-grain dynamic replication schemes for scalable content delivery networks. GLOBECOM 2002: 2235-2239

Makoto Nagata, Yoshitaka Murasaka, Youichi Nishimori, Takashi Morie, Atsushi Iwata: Substrate Noise Analysis with Compact Digital Noise Injection and Substrate Models. VLSI Design 2002: 71-76

Makoto Nagata, Takafumi Ohmoto, Jin Nagai, Takashi Morie, Atsushi Iwata: Test circuits for substrate noise evaluation in CMOS digital ICs. ASP-DAC 2001: 13-14

Yoshitaka Murasaka, Makoto Nagata, Takafumi Ohmoto, Takashi Morie, Atsushi Iwata: Chip-Level Substrate Noise Analysis with Network Reduction by Fundamental Matrix Computation. ISQED 2001: 482-487

Takashi Morie, Tomohiro Matsuura, Makoto Nagata, Atsushi Iwata: An Efficient Clustering Algorithm Using Stochastic Association Model and Its Implementation Using Nanostructures. NIPS 2001: 1115-1122

Rauf Izmailov, Atsushi Iwata, Bhaskar Sengupta: ATM Routing Algorithms for Multimedia Traffic in Private ATM Networks. J. Heuristics 6(1): 21-38 (2000)

Atsushi Iwata, Norihito Fujita: A hierarchical multilayer QoS routing system with dynamic SLA management. IEEE Journal on Selected Areas in Communications 18(12): 2603-2616 (2000)

Makoto Nagata, Jin Nagai, Takashi Morie, Atsushi Iwata: Measurements and analyses of substrate noise waveform inmixed-signal IC environment. IEEE Trans. on CAD of Integrated Circuits and Systems 19(6): 671-678 (2000)

Noriaki Takeda, Mitsuru Homma, Makoto Nagata, Takashi Morie, Atsushi Iwata: A smart imager for the vision processing front-END. ASP-DAC 2000: 19-20

Kenichi Murakoshi, Takashi Morie, Makoto Nagata, Atsushi Iwata: An arbitrary chaos generator core curcuit using PWM/PPM signals. ASP-DAC 2000: 23-24

Makoto Nagata, Atsushi Iwata: Substrate crosstalk analysis in mixed signal CMOS integrated circuits: embedded tutorial. ASP-DAC 2000: 623-630

Atsushi Iwata, Makoto Nagata, Hiroyuki Nakamoto, Noriaki Takeda, Mitsuru Homma, Hiroto Higashi, Takashi Morie: A Feature Associative Processor for Image Recognition Based on A-D merged Architecture. VLSI 1999: 77-88

Souta Sakabayashi, Takashi Morie, Makoto Nagata, Atsushi Iwata: Nonlinear Function Generators and Chaotic Signal Generators Based on Pulse-Phase Modulation. ICONIP 1998: 582-585

Hiroshi Ando, Takashi Morie, Makoto Nagata, Atsushi Iwata: Oscillator Networks for Image Segmentation and Their Circuits Using Pulse Modulation Method. ICONIP 1998: 586-589

Atsushi Iwata, N. Mori, Chinatsu Ikeda, Hiroshi Suzuki, Maximilian Ott: ATM Connection and Traffic Management Schemes for Multimedia Internetworking. Commun. ACM 38(2): 72-89 (1995)