Peter Jamieson

Peter A. Jamieson

	2012
c17		Jonathan Rose, Jason Luu, Chi Wai Yu, Opal Densmore, Jeffrey Goeders, Andrew Somerville, Kenneth B. Kent, Peter Jamieson, Jason Helge Anderson: The VTR project: architecture and CAD for FPGAs from verilog to routing. FPGA 2012: 77-86
	2011
j5		Jason Luu, Ian Kuon, Peter Jamieson, Ted Campbell, Andy Ye, Wei Mark Fang, Kenneth B. Kent, Jonathan Rose: VPR 5.0: FPGA CAD and architecture exploration tools with single-driver routing, heterogeneity and process scaling. TRETS 4(4): 32 (2011)
	2010
j4		Tobias Becker, Peter Jamieson, Wayne Luk, Peter Y. K. Cheung, Tero Rissa: Power Characterisation for Fine-Grain Reconfigurable Fabrics. Int. J. Reconfig. Comp. 2010 (2010)
j3		Peter Jamieson, Tobias Becker, Peter Y. K. Cheung, Wayne Luk, Tero Rissa, Teemu Pitkänen: Benchmarking and evaluating reconfigurable architectures targeting the mobile domain. ACM Trans. Design Autom. Electr. Syst. 15(2) (2010)
j2		Peter A. Jamieson, Jonathan Rose: Enhancing the Area Efficiency of FPGAs With Hard Circuits Using Shadow Clusters. IEEE Trans. VLSI Syst. 18(12): 1696-1709 (2010)
c16		Peter Jamieson: Persistent CAD for in-the-field Power Optimization. ERSA 2010: 267-270
c15		Peter Jamieson, Kenneth B. Kent, Farnaz Gharibian, Lesley Shannon: Odin II - An Open-Source Verilog HDL Synthesis Tool for CAD Research. FCCM 2010: 149-156
c14		Peter Jamieson, Darrel Davis, Brooke Spangler: The Mythical Creature Approach - A Simulation Alternative to Building Computer Architectures. FECS 2010: 23-28
c13		Peter A. Jamieson, Kenneth B. Kent: Odin II: an open-source verilog HDL synthesis tool for FPGA cad flows (abstract only). FPGA 2010: 288
c12		Farnaz Gharibian, Lesley Shannon, Peter Jamieson: Finding System-Level Information and Analyzing Its Correlation to FPGA Placement. FPL 2010: 544-549
c11		Peter Jamieson: Revisiting Genetic Algorithms for the FPGA Placement Problem. GEM 2010: 16-22
	2009
c10		Luke Terry, Vladimir Roitch, Shoeb Tufail, Kirit Singh, Omair Taraq, Wayne Luk, Peter Jamieson: Harnessing Human Computation Cycles for the FPGA Placement Problem. ERSA 2009: 188-194
c9		Peter Jamieson, Tobias Becker, Wayne Luk, Peter Y. K. Cheung, Tero Rissa, Teemu Pitkänen: Benchmarking Reconfigurable Architectures in the Mobile Domain. FCCM 2009: 131-138
c8		Jason Luu, Ian Kuon, Peter Jamieson, Ted Campbell, Andy Ye, Wei Mark Fang, Jonathan Rose: VPR 5.0: FPGA cad and architecture exploration tools with single-driver routing, heterogeneity and process scaling. FPGA 2009: 133-142
	2008
c7		Tobias Becker, Peter Jamieson, Wayne Luk, Peter Y. K. Cheung, Tero Rissa: Towards benchmarking energy efficiency of reconfigurable architectures. FPL 2008: 691-694
	2007
c6		Peter Jamieson, Jonathan Rose: Architecting Hard Crossbars on FPGAs and Increasing their Area Efficiency with Shadow Clusters. FPT 2007: 57-64
	2006
c5		Peter Jamieson, Jonathan Rose: Enhancing the area-efficiency of FPGAs with hard circuits using shadow clusters. FPT 2006: 1-8
	2005
c4		Peter Jamieson, Jonathan Rose: A Verilog RTL Synthesis Tool for Heterogeneous FPGAs. FPL 2005: 305-310
	2003
j1		Angelos Bilas, Courtney R. Gibson, Reza Azimi, Rosalia Christodoulopoulou, Peter Jamieson: Using System Emulation to Model Next-Generation Shared Virtual Memory Clusters. Cluster Computing 6(4): 325-338 (2003)
	2002
c3		Peter Jamieson, Angelos Bilas: CableS: Thread Control and Memory Management Extensions for Shared Virtual Memory Clusters. HPCA 2002: 263-274
	2001
c2		Peter Jamieson, Angelos Bilas: CableS : Thread Control and Memory System Extensions for Shared Virtual Memory Clusters. WOMPAT 2001: 170-184
	2000
c1		Kathy Lynch, Angela Carbone, Peter Jamieson, David Arnott: Adopting a studio-based education approach into information technology (poster session). ACSE 2000: 254

Coauthor Index

Colors in the list of coauthors

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